Method for Forming Self-Aligned Trench Contacts of Semiconductor Components and A Semiconductor Component

• US 20130181284A1
• Filed: 01/16/2012
• Published: 07/18/2013
• Est. Priority Date: 01/16/2012
• Status: Active Grant

• Current Assignee: Infineon Technologies Austria Ag (Infineon Technologies AG)
• Original Assignee: Infineon Technologies Austria Ag (Infineon Technologies AG)
• Inventors: Poelzl, Martin
• Granted Patent: US 9,082,746 B2
• Time in Patent Office: Days
• US Class Current: 257/332
• CPC Class Codes: H01L 21/0337 characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
• CPC Class Codes: H01L 21/308 using masks H01L21/3063, H01L21/3065 take precedence
• CPC Class Codes: H01L 21/31144 using masks
• CPC Class Codes: H01L 21/76897 Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step self-aligned silicidation on field effect transistors H01L29/665
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/40114 the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41708 Emitter or collector electrodes for bipolar transistors
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/6634 with a recess formed by etching in the source/emitter contact region H01L29/66348 takes precedence; etching of semiconductor bodies H01L21/302
• CPC Class Codes: H01L 29/66348 with a recessed gate
• CPC Class Codes: H01L 29/66719 With a step of forming an insulating sidewall spacer
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A method for producing a semiconductor component is described. The method includes providing a semiconductor body having a first surface and being comprised of a first semiconductor material extending to the first surface. At least one trench extends from the first surface into the semiconductor body and includes a gate electrode insulated from the semiconductor body and arranged below the first surface. The method further includes: forming a second insulation layer on the first surface with a recess that overlaps in projection onto the first surface with the conductive region; forming a mask region in the recess; etching the second insulation layer selectively to the mask region and the semiconductor body to expose the semiconductor body at the first surface; depositing a third insulation layer on the first surface; and etching the third insulation layer so that a semiconductor mesa of the semiconductor body arranged next to the a least one trench is exposed at the first surface.

Claims

1. A method for producing a semiconductor component, comprising:

providing a semiconductor arrangement comprising;

a semiconductor body comprising a first semiconductor material extending to a first surface and at least one trench extending from the first surface, the at least one trench comprising a conductive region insulated from the semiconductor body and arranged below the first surface;

forming a second insulation layer on the first surface comprising a recess that overlaps in a projection onto the first surface with the conductive region;

forming a mask region in the recess; and

etching the second insulation layer selectively to the mask region and the semiconductor body to expose the semiconductor body at the first surface;

depositing a third insulation layer on the first surface; and

etching the third insulation layer so that a semiconductor mesa of the semiconductor body arranged next to the at least one trench is exposed at the first surface.

2. The method of claim 1, wherein the at least one trench comprises, in a cross-section substantially orthogonal to the first surface, two side walls, and wherein the second insulation layer is, after etching the second insulation layer and in the projection onto the first surface, arranged within the two side walls.

3. The method of claim 1, wherein the second insulation layer is formed as a TEOS or a HDP-oxide.

4. The method of claim 1, wherein the second insulation layer is mask-less deposited.

5. The method of claim 1, wherein etching the second insulation layer comprises anisotropic etching.

6. The method of claim 1, wherein etching the second insulation layer comprises selective etching the second insulation layer in a process having an etching rate of the second insulation layer that is at least 10 times higher than an etching rate of the mask region.

7. The method of claim 1, wherein forming the mask region comprises at least one of:

depositing poly-silicon and a CMP-process.

8. The method of claim 1, wherein forming the mask region comprises at least one of:

depositing a dielectric material; and

back etching the dielectric material selective to the second insulation layer.

9. The method of claim 1, wherein the mask region is formed as a nitride.

10. The method of claim 1, wherein the third insulation layer is formed by conformal deposition.

11. The method of claim 1, wherein the third insulation layer is formed as a layer comprised of TEOS, USG or doped silicon oxide.

12. The method of claim 1, wherein etching the third insulation layer comprises anisotropic etching.

13. The method of claim 1, wherein the semiconductor arrangement further comprises at least one of:

a field electrode formed in a lower portion of the at least one trench and being insulated from the semiconductor body by the first insulation layer;

a gate dielectric region formed such that the gate dielectric region at least lines side walls of the at least one trench in an upper portion; and

a gate electrode formed by the conductive region and arranged on and being insulated from the field electrode in the at least one trench.

14. The method of claim 1, further comprising prior to forming the second insulation layer at least one of:

forming a source region or an emitter region next to the at least one trench and extending to the first surface; and

forming a body region next to the at least one trench, the body region forming two pn-junctions with adjoining semiconductor regions within the semiconductor body.

15. The method of claim 14, further comprising at least one of:

forming a shallow trench in the semiconductor body next to the at least one trench for contacting at least one of the source region, the emitter region and the body region; and

forming a metallization in electric contact with at least one of the source region, the emitter region and the body region.

16. A method for producing a semiconductor component, comprising:

providing a semiconductor arrangement comprising;

a semiconductor body comprising a first semiconductor material extending to a first surface and at least one trench extending from the first surface, the at least one trench comprising a gate electrode insulated from the semiconductor body and arranged below the first surface;

depositing an insulation layer on the first surface and the gate electrode so that the insulation layer comprises a recess that is, in a projection onto the first surface, completely arranged within the at least one trench; and

filling the recess with a non-crystalline form of the first semiconductor material to form a mask region.

17. The method of claim 16, further comprising anisotropic etching the insulation layer using the mask region as a mask to expose the semiconductor body at the first surface.

18. The method of claim 17, further comprising forming a contact in a self-aligned manner to at least one of a source region, an emitter region and a body region formed in a semiconductor mesa next to the at least one trench, comprising at least one of:

depositing a further insulation layer on the first surface and on the mask region; and

anisotropic etching of the further insulation layer to expose the semiconductor mesa and to form an insulation structure arranged on the gate electrode and extending above the first surface; and

etching shallow contact trenches next to the at least one trench using the insulation structure as a mask.

19. A method for producing a semiconductor component, comprising:

providing a semiconductor arrangement comprising;

a semiconductor body comprising a first semiconductor material extending to a first surface and at least one trench extending from the first surface, the at least one trench comprising a gate electrode insulated from the semiconductor body and arranged below the first surface;

depositing an insulation layer on the first surface and the gate electrode so that the insulation layer comprises a recess which is, in a projection onto the first surface, completely arranged within the at least one trench; and

forming a mask region comprising depositing a dielectric material on the insulation layer and plasma etching the dielectric material using the insulation layer as an etch-stop.

20. The method of claim 19, further comprising anisotropic etching the insulation layer using the mask region as a mask to expose the semiconductor body at the first surface.

21. The method of claim 20, further comprising forming a contact in a self-aligned manner to at least one of a source region, an emitter region and a body region formed in a semiconductor mesa next to the at least one trench, comprising at least one of:

depositing a further insulation layer on the first surface and on the mask region;

anisotropic etching of the further insulation layer to expose the semiconductor mesa and to form an insulation structure arranged on the gate electrode and extending above the first surface; and

etching shallow contact trenches next to the at least one trench using the insulation structure as a mask.

22. A field effect semiconductor component, comprising:

a semiconductor body having a first surface defining a vertical direction;

at least one trench extending from the first surface into the semiconductor body and comprising a gate electrode arranged below the first surface and being insulated from the semiconductor body;

a first metallization arranged on the first surface and in electric contact with the semiconductor body; and

an insulation structure arranged between the gate electrode and the first metallization, the insulation structure comprising a silicon oxide layer adjoining an upper surface of the gate electrode, extending above the first surface and comprising a recess completely arranged within the gate electrode when seen from above, the insulation structure further comprising a silicon nitride region arranged in the recess and between the silicon oxide layer and the first metallization.

23. The field effect semiconductor component of claim 22, wherein the insulating structure has, in a vertical cross-section, a width which is about 50 nm to about 100 nm larger than a width of an uppermost portion of the at least one trench.

24. The field effect semiconductor component of claim 22, further comprising an insulated field electrode arranged in a lower portion of the at least one trench and below the gate electrode.

25. The field effect semiconductor component of claim 22, wherein the silicon oxide layer comprises at least one of:

a first silicon oxide region arranged below the silicon nitride region and comprised of one of TEOS and a HDP-oxide; and

a second silicon oxide region arranged between the first silicon oxide region and the first metallization and comprised of at least one of TEOS, USG and a doped oxide.