SEMICONDUCTOR INTEGRATED CIRCUIT AND OPERATING METHOD THEREOF

• US 20130182804A1
• Filed: 01/16/2013
• Published: 07/18/2013
• Est. Priority Date: 01/18/2012
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Renesas Electronics Corporation
• Inventors: Yutaka, Igarashi, Yusaku, Katsube
• Granted Patent: US 8,842,719 B2
• Time in Patent Office: Days
• US Class Current: 375/347
• CPC Class Codes: H04B 1/006 using switches for selecting the desired band H04B1/0057 takes precedence
• CPC Class Codes: H04B 1/30 for homodyne or synchrodyne receivers demodulator circuits H03D1/22
• CPC Class Codes: H04B 1/406 with more than one transmission mode, e.g. analog and digital modes
• CPC Class Codes: H04L 27/0002 analog front ends; means for connecting modulators, demodulators or transceivers to a transmission line duplex arrangements H04L5/143
• CPC Class Codes: H04L 27/2272 using phase locked loops H04L27/2273 takes precedence

Abstract

To reduce the time of reception operation switching between multiple wireless systems, a semiconductor integrated circuit includes a first reception unit including a first analog reception unit and a first digital reception unit, and a digital interface. The first analog reception unit includes a first reception mixer and a first A/D converter, and the first digital reception unit includes a first digital filter. The first reception unit, an oscillator, and a PLL enable switching from a reception operation for a first RF reception signal of a first system to a reception operation for a second RF reception signal of a second system. In a period of an end transition operation of the first digital reception unit in the switching, the PLL starts a lock operation so as to match a frequency of an oscillation output signal generated from the oscillator to a desired frequency of the second system.

Claims

1. A semiconductor integrated circuit comprising:

a first wireless access system reception unit comprising a first analog reception unit and a first digital reception unit;

a voltage-controlled oscillator;

a phase locked loop; and

a digital interface,

wherein the first analog reception unit comprises a first reception mixer for down-converting an RF reception signal into a first analog reception signal and a first analog-digital converter for converting the first analog reception signal into a first digital reception signal,

wherein the first digital reception unit comprises a first digital filter having an input terminal to which the first digital reception signal is supplied,

wherein a first digital filter reception output signal outputted from an output terminal of the first digital filter in the first digital reception unit can be outputted to an outside of the semiconductor integrated circuit through the digital interface,

wherein the voltage-controlled oscillator generates an oscillation output signal as a base for a first reception local signal supplied to the first reception mixer, and the phase locked loop locks a frequency of the oscillation output signal generated from the voltage-controlled oscillator to a desired frequency,

wherein the first wireless access system reception unit, the voltage-controlled oscillator, and the phase locked loop enable switching from a reception operation for a first RF reception signal of a first system to a reception operation for a second RF reception signal of a second system,

wherein in the switching, as for the reception operation for the first RF reception signal of the first system, an end transition operation of the first digital reception unit is performed subsequent to an end transition operation of the first analog reception unit,

wherein in the switching, for the reception operation for the second RF reception signal of the second system, a start transition operation of the first analog reception unit and a start transition operation of the first digital reception unit are performed, and

wherein in a period of the end transition operation of the first digital reception unit in the switching, the phase locked loop starts a lock operation so as to match a frequency of the oscillation output signal generated from the voltage-controlled oscillator to a desired frequency of the second system.

2. The semiconductor integrated circuit according to claim 1, further comprising a second wireless access system reception unit comprising a second analog reception unit and a second digital reception unit,

wherein the second analog reception unit comprises a second reception mixer for down-converting an RF reception signal into a second analog reception signal and a second analog-digital converter for converting the second analog reception signal into a second digital reception signal,

wherein the second digital reception unit comprises a second digital filter having an input terminal to which the second digital reception signal is supplied,

wherein a second digital filter reception output signal outputted from an output terminal of the second digital filter in the second digital reception unit can be outputted to the outside of the semiconductor integrated circuit through the digital interface,

wherein the voltage-controlled oscillator generates an oscillation output signal as a base for the first reception local signal supplied to the first reception mixer, and the phase locked loop locks a frequency of the oscillation output signal generated from the voltage-controlled oscillator to a desired frequency of the first system,

wherein the voltage-controlled oscillator generates an oscillation output signal as a base for a second reception local signal supplied to the second reception mixer, and the phase locked loop locks a frequency of the oscillation output signal generated from the voltage-controlled oscillator to a desired frequency of the second system,

wherein the first wireless access system reception unit, the voltage-controlled oscillator, and the phase locked loop can perform the reception operation for the first RF reception signal of the first system,

wherein the second wireless access system reception unit, the voltage-controlled oscillator, and the phase locked loop can perform the reception operation for the second RF reception signal of the second system,

wherein the first wireless access system reception unit, the second wireless access system reception unit, the voltage-controlled oscillator, and the phase locked loop enable switching from the reception operation for the first RF reception signal of the first system to the reception operation for the second RF reception signal of the second system,

wherein in the switching, as for the reception operation for the first RF reception signal of the first system, the end transition operation of the first digital reception unit is performed subsequent to the end transition operation of the first analog reception unit,

wherein in the switching, for the reception operation for the second RF reception signal of the second system, a start transition operation of the second analog reception unit and a start transition operation of the second digital reception unit are performed, and

wherein in a period of the end transition operation of the first digital reception unit in the switching, the phase locked loop starts a lock operation so as to match the frequency of the oscillation output signal generated from the voltage-controlled oscillator to the desired frequency of the second system.

3. The semiconductor integrated circuit according to claim 2, wherein the first digital filter and the second digital filter are each comprised of multiple FIR filters.

4. The semiconductor integrated circuit according to claim 3, further comprising a first wireless access system transmission unit comprising a first digital transmission unit and a first analog transmission unit and a second wireless access system transmission unit comprising a second digital transmission unit and a second analog transmission unit,

wherein the first digital transmission unit of the first wireless access system transmission unit can convert a first digital transmission signal of the first system supplied from the outside of the semiconductor integrated circuit through the digital interface into a first analog transmission signal,

wherein the second digital transmission unit of the second wireless access system transmission unit can convert a second digital transmission signal of the second system supplied from the outside of the semiconductor integrated circuit through the digital interface into a second analog transmission signal,

wherein the first analog transmission unit of the first wireless access system transmission unit can up-convert the first analog transmission signal into a first RF transmission signal of the first system, and

wherein the second analog transmission unit of the second wireless access system transmission unit can up-convert the second analog transmission signal into a second RF transmission signal of the second system.

5. The semiconductor integrated circuit according to claim 3, wherein a sampling rate of the first analog-digital converter and the second analog-digital converter is set to be higher than a sampling rate of a digital interface output terminal of the digital interface, and

wherein the first digital filter and the second digital filter also function as asynchronous sampling rate converters for converting the sampling rate of the first analog-digital converter and the second analog-digital converter into the sampling rate of the digital interface output terminal of the digital interface.

6. The semiconductor integrated circuit according to claim 3, further comprising a control unit for performing switching between the reception operation for the first RF reception signal of the first system and the reception operation for the second RF reception signal of the second system,

wherein the control unit can store a signal delay time of the first analog reception unit and the second analog reception unit and a signal delay time of the first digital reception unit and the second digital reception unit.

7. The semiconductor integrated circuit according to claim 3,

wherein the first analog reception unit further comprises a first low noise amplifier, a first variable analog filter, and a first analog variable gain amplifier,

wherein the first low noise amplifier supplies the first RF reception signal of the first system to the first reception mixer, and the first variable analog filter and the first analog variable gain amplifier are coupled in series between an output of the first reception mixer and an input of the first analog-digital converter,

wherein the second analog reception unit further comprises a second low noise amplifier, a second variable analog filter, and a second analog variable gain amplifier, and

wherein the second low noise amplifier supplies the second RF reception signal of the second system to the second reception mixer, and the second variable analog filter and the second analog variable gain amplifier are coupled in series between an output of the second reception mixer and an input of the second analog-digital converter.

8. The semiconductor integrated circuit according to claim 7, wherein in the period of the end transition operation of the first digital reception unit in the switching, the second analog reception unit of the second wireless access system reception unit cancels DC offset voltage and calibrates a filter characteristic of the second variable analog filter, concurrently with the start of the lock operation of the phase locked loop.

9. The semiconductor integrated circuit according to claim 8, wherein an input terminal of the first low noise amplifier in the first wireless access system reception unit and an input terminal of the second low noise amplifier in the second wireless access system reception unit can be coupled to a front-end module coupled to an antenna for receiving the first RF reception signal of the first system and the second RF reception signal of the second system.

10. The semiconductor integrated circuit according to claim 9, wherein the first RF transmission signal of the first system generated from the first analog transmission unit of the first wireless access system transmission unit can be supplied to the antenna through a first RF power amplifier and the front-end module, and

wherein the second RF transmission signal of the second system generated from the second analog transmission unit of the second wireless access system transmission unit can be supplied to the antenna through a second RF power amplifier and the front-end module.

11. An operating method of a semiconductor integrated circuit comprising a first wireless access system reception unit comprising a first analog reception unit and a first digital reception unit, a voltage-controlled oscillator, a phase locked loop, and a digital interface,

the first analog reception unit comprising a first reception mixer for down-converting an RF reception signal into a first analog reception signal and a first analog-digital converter for converting the first analog reception signal into a first digital reception signal,

the first digital reception unit comprising a first digital filter having an input terminal to which the first digital reception signal is supplied,

the operating method comprising the steps of:

outputting a first digital filter reception output signal outputted from an output terminal of the first digital filter in the first digital reception unit to an outside of the semiconductor integrated circuit through the digital interface;

generating by the voltage-controlled oscillator an oscillation output signal as a base for a first reception local signal supplied to the first reception mixer, and locking by the phase locked loop a frequency of the oscillation output signal generated from the voltage-controlled oscillator to a desired frequency; and

performing, by the first wireless access system reception unit, the voltage-controlled oscillator, and the phase locked loop, switching from a reception operation for a first RF reception signal of a first system to a reception operation for a second RF reception signal of a second system,

wherein in the switching, as for the reception operation for the first RF reception signal of the first system, an end transition operation of the first digital reception unit is performed subsequent to an end transition operation of the first analog reception unit,

wherein in the switching, for the reception operation for the second RF reception signal of the second system, a start transition operation of the first analog reception unit and a start transition operation of the first digital reception unit are performed, and

wherein in a period of the end transition operation of the first digital reception unit in the switching, the phase locked loop starts a lock operation so as to match a frequency of the oscillation output signal generated from the voltage-controlled oscillator to a desired frequency of the second system.

12. The operating method of the semiconductor integrated circuit according to claim 11,

the semiconductor integrated circuit further comprising a second wireless access system reception unit comprising a second analog reception unit and a second digital reception unit,

the second analog reception unit comprising a second reception mixer for down-converting an RF reception signal into a second analog reception signal and a second analog-digital converter for converting the second analog reception signal into a second digital reception signal,

the second digital reception unit comprising a second digital filter having an input terminal to which the second digital reception signal is supplied,

the operating method further comprising the steps of:

outputting a second digital filter reception output signal outputted from an output terminal of the second digital filter in the second digital reception unit to the outside of the semiconductor integrated circuit through the digital interface;

generating by the voltage-controlled oscillator an oscillation output signal as a base for the first reception local signal supplied to the first reception mixer, and locking by the phase locked loop a frequency of the oscillation output signal generated from the voltage-controlled oscillator to a desired frequency of the first system;

generating by the voltage-controlled oscillator an oscillation output signal as a base for a second reception local signal supplied to the second reception mixer, and locking by the phase locked loop a frequency of the oscillation output signal generated from the voltage-controlled oscillator to a desired frequency of the second system;

performing, by the first wireless access system reception unit, the voltage-controlled oscillator, and the phase locked loop, the reception operation for the first RF reception signal of the first system;

performing, by the second wireless access system reception unit, the voltage-controlled oscillator, and the phase locked loop, the reception operation for the second RF reception signal of the second system; and

performing, by the first wireless access system reception unit, the second wireless access system reception unit, the voltage-controlled oscillator, and the phase locked loop, switching from the reception operation for the first RF reception signal of the first system to the reception operation for the second RF reception signal of the second system,

wherein in the switching, as for the reception operation for the first RF reception signal of the first system, the end transition operation of the first digital reception unit is performed subsequent to the end transition operation of the first analog reception unit,

wherein in the switching, for the reception operation for the second RF reception signal of the second system, a start transition operation of the second analog reception unit and a start transition operation of the second digital reception unit are performed, and

wherein in a period of the end transition operation of the first digital reception unit in the switching, the phase locked loop starts a lock operation so as to match the frequency of the oscillation output signal generated from the voltage-controlled oscillator to the desired frequency of the second system.

13. The operating method of the semiconductor integrated circuit according to claim 12, wherein the first digital filter and the second digital filter are each comprised of multiple FIR filters.

14. The operating method of the semiconductor integrated circuit according to claim 13,

the semiconductor integrated circuit further comprising a first wireless access system transmission unit comprising a first digital transmission unit and a first analog transmission unit and a second wireless access system transmission unit comprising a second digital transmission unit and a second analog transmission unit,

the operating method further comprising the steps of:

converting, by the first digital transmission unit of the first wireless access system transmission unit, a first digital transmission signal of the first system supplied from the outside of the semiconductor integrated circuit through the digital interface into a first analog transmission signal;

converting, by the second digital transmission unit of the second wireless access system transmission unit, a second digital transmission signal of the second system supplied from the outside of the semiconductor integrated circuit through the digital interface into a second analog transmission signal;

up-converting, by the first analog transmission unit of the first wireless access system transmission unit, the first analog transmission signal into a first RF transmission signal of the first system, and

up-converting, by the second analog transmission unit of the second wireless access system transmission unit the second analog transmission signal into a second RF transmission signal of the second system.

15. The operating method of the semiconductor integrated circuit according to claim 13, wherein a sampling rate of the first analog-digital converter and the second analog-digital converter is set to be higher than a sampling rate of a digital interface output terminal of the digital interface,

wherein the first digital filter and the second digital filter also function as asynchronous sampling rate converters for converting the sampling rate of the first analog-digital converter and the second analog-digital converter into the sampling rate of the digital interface output terminal of the digital interface.

16. The operating method of the semiconductor integrated circuit according to claim 13,

the semiconductor integrated circuit further comprising a control unit for performing switching between the reception operation for the first RF reception signal of the first system and the reception operation for the second RF reception signal of the second system,

the operating method further comprising the step of:

storing by the control unit a signal delay time of the first analog reception unit and the second analog reception unit and a signal delay time of the first digital reception unit and the second digital reception unit.

17. The operating method of the semiconductor integrated circuit according to claim 13, wherein the first analog reception unit further comprises a first low noise amplifier, a first variable analog filter, and a first analog variable gain amplifier,

wherein the first low noise amplifier supplies the first RF reception signal of the first system to the first reception mixer, and the first variable analog filter and the first analog variable gain amplifier are coupled in series between an output of the first reception mixer and an input of the first analog-digital converter,

wherein the second analog reception unit further comprises a second low noise amplifier, a second variable analog filter, and a second analog variable gain amplifier, and

wherein the second low noise amplifier supplies the second RF reception signal of the second system to the second reception mixer, and the second variable analog filter and the second analog variable gain amplifier are coupled in series between an output of the second reception mixer and an input of the second analog-digital converter.

18. The operating method of the semiconductor integrated circuit according to claim 17, wherein in the period of the end transition operation of the first digital reception unit in the switching, the second analog reception unit of the second wireless access system reception unit cancels DC offset voltage and calibrates a filter characteristic of the second variable analog filter, concurrently with the start of the lock operation of the phase locked loop.

19. The operating method of the semiconductor integrated circuit according to claim 18, wherein an input terminal of the first low noise amplifier in the first wireless access system reception unit and an input terminal of the second low noise amplifier in the second wireless access system reception unit can be coupled to a front-end module coupled to an antenna for receiving the first RF reception signal of the first system and the second RF reception signal of the second system.

20. The operating method of the semiconductor integrated circuit according to claim 19, further comprising the steps of:

supplying the first RF transmission signal of the first system generated from the first analog transmission unit of the first wireless access system transmission unit to the antenna through a first RF power amplifier and the front-end module; and

supplying the second RF transmission signal of the second system generated from the second analog transmission unit of the second wireless access system transmission unit to the antenna through a second RF power amplifier and the front-end module.