SEMICONDUCTOR CHIP AND METHOD OF CONTROLLING MEMORY

• US 20130185525A1
• Filed: 12/21/2012
• Published: 07/18/2013
• Est. Priority Date: 12/27/2011
• Status: Active Grant

• Current Assignee: Foundation of Soongsil University-Industry Cooperation
• Original Assignee: Foundation of Soongsil University-Industry Cooperation
• Inventors: LEE, Chan-Ho
• Granted Patent: US 9,378,125 B2
• Time in Patent Office: Days
• US Class Current: 711/151
• CPC Class Codes: G06F 12/00 Accessing, addressing or allocating within memory systems or architectures digital input from, or digital output to record carriers, e.g. to disk storage units, G06F3/06
• CPC Class Codes: G06F 13/1621 by maintaining request order
• CPC Class Codes: G06F 13/1631 through address comparison
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

Disclosed herein are a semiconductor chip for adaptively processing a plurality of commands to request memory access, and a method of controlling memory. The semiconductor chip includes a storage unit ad a control unit. The storage unit stores a memory access request to be currently processed and a plurality of memory access requests received before the memory access request to be currently processed in received order. The control unit processes the memory access request to be currently processed and the plurality of memory access requests received before the memory access request to be currently processed, which have been stored in the storage unit, in received order, except that memory access requests attempting to access the same bank and the same row are successively processed.

Claims

1. A semiconductor chip for adaptively processing a plurality of commands to request memory access, comprising:

a storage unit configured to store a memory access request to be currently processed and a plurality of memory access requests received before the memory access request to be currently processed in received order; and

a control unit configured to process the memory access request to be currently processed and the plurality of memory access requests received before the memory access request to be currently processed, which have been stored in the storage unit, in received order, except that memory access requests attempting to access a same bank and a same row are successively processed.

2. The semiconductor chip of claim 1, wherein the control unit comprises:

an inquiry unit configured to sequentially inquiry memory addresses that the memory access request to be currently processed and the plurality of memory access requests received before the memory access request to be currently processed attempt to access, in reverse order; and

a re-ordering unit configured to, if it is determined that there is a request attempting to access a same bank and a same row as the memory access request to be currently processed based on the memory addresses inquired in reverse order, place the memory access request to be currently processed after the request attempting to access the same bank and the same row.

3. The semiconductor chip of claim 2, wherein the re-ordering unit, if there is a plurality of successive requests attempting to access the same bank and the same row as the memory access request to be currently processed, places the memory access request to be currently processed after a last request of the successive requests.

4. The semiconductor chip of claim 1, wherein the control unit comprises:

an inquiry unit configured to sequentially inquire memory addresses that the memory access request to be currently processed and the plurality of memory access requests received before the memory access request to be currently processed attempt to access, in reverse order; and

a re-ordering unit configured to, if it is determined that there is no request attempting to access a same bank and a same row as the memory access request to be currently processed based on the memory addresses inquired in reverse order, compare a memory address that an n-th request which is the last memory access request in the storage unit attempts to access with a memory address that an (n−

1)-th request attempts to access, and place the memory access request to be currently processed before the n-th request if the addresses are mapped to different rows of a same bank and the banks that the n-th request and the memory access request to be currently processed attempt to access are different.

5. The semiconductor chip of claim 1, wherein the control unit comprises:

an inquiry unit configured to sequentially inquire memory addresses that the memory access request to be currently processed and the plurality of memory access requests received before the memory access request to be currently processed attempt to access, in reverse order; and

an re-ordering unit configured to, if it is determined that there is no request attempting to access a same bank and a same row as the memory access request to be currently processed based on the memory addresses inquired in reverse order, compare a memory address that an n-th request which is the last memory access request in the storage unit attempts to access with a memory address that an (n−

1)-th request attempts to access, compare an (n−

1)-th request with its previous requests if the addresses are mapped to different rows of a same bank and the banks that the n-th request and the memory access request to be currently processed attempt to access are identical, place the (n−

1)-th request before a closest request attempting to access a bank different from a bank that the (n−

1)-th request attempts to access and place the memory access request to be currently processed after the n-th request.

6. The semiconductor chip of claim 1, wherein the control unit comprises:

an inquiry unit configured to sequentially inquire memory addresses that the memory access request to be currently processed and the plurality of memory access requests received before the memory access request to be currently processed attempt to access, in reverse order; and

an re-ordering unit configured to, if it is determined that there is no request attempting to access a same bank and a same row as the memory access request to be currently processed based on the memory addresses inquired in reverse order, compare a memory address that an n-th request which is the last memory access request in the storage unit attempts to access with a memory address that an (n−

1)-th request attempts to access, and place the memory access request to be currently processed after the n-th request if the banks that the n-th request and the (n−

1)-th request attempt to access are different.

7. The semiconductor chip of claim 2, wherein the re-ordering unit, if there is a first QoS request guaranteeing data transmission bandwidth, places the first QoS request in a foremost part of the storage unit in order to process the first QoS request earlier than the plurality of memory access requests, and places the first QoS request after a second QoS request if there is a second QoS request received before the first QoS request.

8. The semiconductor chip of claim 3, wherein if there are successive requests attempting to access the same bank and the same row as the memory access request to be currently processed and a number of successive requests exceeds a preset number, the memory access request to be currently processed is placed in received order.

9. A method of controlling memory, the method being performed by an apparatus for controlling semiconductor chip memory for adaptively processing a plurality of commands to request memory access, the method comprising the steps of:

(a) storing a memory access request to be currently processed and a plurality of memory access requests received before the memory access request to be currently processed in a storage unit in received order, and inquiring memory addresses that the requests attempt to access sequentially in reverse order; and

(b) if it is determined that there is a request attempting to access a same bank and a same row as the memory access request to be currently processed based on the memory addresses inquired in reverse order, placing the memory access request to be currently processed after the request attempting to access the same bank and the same row.

10. The method of claim 9, wherein step (b) comprises the step of, if there is a plurality of successive requests attempting to access the same bank and the same row as the memory access request to be currently processed, placing the memory access request to be currently processed after a last request of the successive requests.

11. The method of claim 9, wherein step (b) comprises the step of, if it is determined that there is no request attempting to access a same bank and a same row as the memory access request to be currently processed, comparing a memory address that an n-th request which is the last memory access request in the storage unit attempts to access with a memory address that an (n−

1)-th request attempts to access, and placing the memory access request to be currently processed before the n-th request if the addresses are mapped to different rows of a same bank and the banks that the n-th request and the memory access request to be currently processed attempt to access are different.

12. The method of claim 9, wherein step (b) comprises the step of, if it is determined that there is no request attempting to access a same bank and a same row as the memory access request to be currently processed, comparing a memory address that an n-th request which is the last memory access request in the storage unit attempts to access with a memory address that an (n−

1)-th request attempts to access, comparing an (n−

1)-th request with its previous requests if the addresses are mapped to different rows of a same bank and the banks that the n-th request and the memory access request to be currently processed attempt to access are identical, and placing the (n−

1)-th request before a closest request attempting to access a bank different from a bank that the (n−

1)-th request attempts to access and placing the memory access request to be currently processed after the n-th request.

13. The method of claim 9, wherein step (b) comprises the step of, if it is determined that there is no request attempting to access a same bank and a same row as the memory access request to be currently processed based on the memory addresses inquired in reverse order, comparing a memory address that an n-th request which is the last memory access request in the storage unit attempts to access with a memory address that an (n−

1)-th request attempts to access, and placing the memory access request to be currently processed after the n-th request if the banks that the n-th request and the (n−

1)-th request attempt to access are different.

14. The method of claim 9, further comprising the step of, if there is a first QoS request guaranteeing data transmission bandwidth, placing the first QoS request in a foremost part of the storage unit in order to process the first QoS request earlier than the plurality of normal memory access requests, and placing the first QoS request after a second QoS request if there is the second QoS request received before the first QoS request.

15. The method of claim 10, wherein step (b) comprises the step of, if there are successive requests attempting to access the same bank and the same row as the memory access request to be currently processed and a number of successive requests exceeds a preset number, placing the memory access request to be currently processed in received order.