IMAGERS HAVING VARIABLE GAIN AND RELATED STRUCTURES AND METHODS
First Claim
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1. A readout integrated circuit (ROIC), comprising:
- a memory configured to store, for each of a plurality of temperatures, a plurality of integration period scaling factors including a first integration period scaling factor corresponding to at least one first row of an array of imaging pixels and a second integration period scaling factor corresponding to at least one second row of the array of imaging pixels;
a plurality of multipliers, each multiplier of the plurality of multipliers configured to;
receive a nominal integration period value;
receive one of the plurality of integration period scaling factors; and
scale the nominal integration period value by the one of the plurality of integration period scaling factors to produce a corresponding scaled integration period value; and
a plurality of pulse generators including one pulse generator corresponding to each row of the array of imaging pixels,wherein each of the plurality of pulse generators is configured to receive a scaled integration period value from a multiplier of the plurality of multipliers and generate one or more timing signals based on the received scaled integration period value, wherein the one or more timing signals control, at least in part, a duration of an integration period of imaging pixels in a corresponding row of the array of imaging pixels.
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Abstract
The present application relates to imagers having variable gain and related structures and methods. The gain of the imager may vary between rows of the imager. Such variability may be achieved by suitable design of a readout integrated circuit (ROIC). The ROIC may provide different integration period durations for different rows of the imager. Different integration capacitances may be provided for pixels of different rows of the imager. The gain of a column buffer may be varied when operating on output signals of pixels from different rows.
9 Citations
33 Claims
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1. A readout integrated circuit (ROIC), comprising:
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a memory configured to store, for each of a plurality of temperatures, a plurality of integration period scaling factors including a first integration period scaling factor corresponding to at least one first row of an array of imaging pixels and a second integration period scaling factor corresponding to at least one second row of the array of imaging pixels; a plurality of multipliers, each multiplier of the plurality of multipliers configured to; receive a nominal integration period value; receive one of the plurality of integration period scaling factors; and scale the nominal integration period value by the one of the plurality of integration period scaling factors to produce a corresponding scaled integration period value; and a plurality of pulse generators including one pulse generator corresponding to each row of the array of imaging pixels, wherein each of the plurality of pulse generators is configured to receive a scaled integration period value from a multiplier of the plurality of multipliers and generate one or more timing signals based on the received scaled integration period value, wherein the one or more timing signals control, at least in part, a duration of an integration period of imaging pixels in a corresponding row of the array of imaging pixels. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A readout integrated circuit (ROIC), comprising:
circuitry configured to provide an imaging array having multiple rows of imaging pixels with different gains for at least two rows of the multiple rows. - View Dependent Claims (10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23)
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24. A method of operating a readout integrated circuit (ROIC), the method comprising:
generating differences in gain between at least two different rows of an imaging array. - View Dependent Claims (25, 26, 27, 28, 29, 30)
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31. A readout integrated circuit (ROIC), comprising:
an integration clock generator configured to produce respective integration signals for at least two rows of an imager, wherein at least a first and second of the respective integration signals have different durations. - View Dependent Claims (32, 33)
Specification