MEMORY CELLS HAVING HEATERS WITH ANGLED SIDEWALLS

• US 20130187120A1
• Filed: 01/20/2012
• Published: 07/25/2013
• Est. Priority Date: 01/20/2012
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Redaelli, Andrea, Servalli, Giorgio, Petruzza, Pietro, Perrone, Cinzia
• Granted Patent: US 8,962,384 B2
• Time in Patent Office: Days
• US Class Current: 257/5
• CPC Class Codes: H10B 63/80 Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays
• CPC Class Codes: H10B 63/82 the switching components having a common active material layer
• CPC Class Codes: H10N 70/011 Manufacture or treatment of multistable switching devices
• CPC Class Codes: H10N 70/231 based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect
• CPC Class Codes: H10N 70/235 between different crystalline phases, e.g. cubic and hexagonal
• CPC Class Codes: H10N 70/826 adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
• CPC Class Codes: H10N 70/8265 on sidewalls of dielectric structures, e.g. mesa or cup type devices
• CPC Class Codes: H10N 70/8413 adapted for resistive heating
• CPC Class Codes: H10N 70/8613 Heating or cooling means other than resistive heating electrodes, e.g. heater in parallel
• CPC Class Codes: H10N 70/8822 Sulfides, e.g. CuS
• CPC Class Codes: H10N 70/8825 Selenides, e.g. GeSe
• CPC Class Codes: H10N 70/8828 Tellurides, e.g. GeSbTe
• CPC Class Codes: H10N 70/884 Other compounds of groups 13-15, e.g. elemental or compound semiconductors

Abstract

Memory cells having heaters with angled sidewalls and methods of forming the same are described herein. As an example, a method of forming an array of resistive memory cells can include forming a first resistive memory cell having a first heater element angled with respect to a vertical plane, forming a second resistive memory cell adjacent to the first resistive memory cell and having a second heater element angled with respect to the vertical plane and toward the first heater, and forming a third resistive memory cell adjacent to the first resistive memory cell and having a third heater element angled with respect to the vertical plane and away from the first heater element.

Claims

1. A method of forming an array of resistive memory cells, the method comprising:

forming a first resistive memory cell having a first heater element angled with respect to a vertical plane;

forming a second resistive memory cell adjacent to the first resistive memory cell and having a second heater element angled with respect to the vertical plane and toward the first heater; and

forming a third resistive memory cell adjacent to the first resistive memory cell and having a third heater element angled with respect to the vertical plane and away from the first heater element.

2. The method claim 1, wherein forming the first heater element, the second heater element, and the third heater element includes forming L-shaped heater elements having a horizontal base portion and a vertically angled wall portion.

3. The method claim 1, wherein forming the first resistive memory cell and the second resistive memory cell includes forming front to front memory cells.

4. The method claim 1, wherein forming the first resistive memory cell and the third resistive memory cell includes forming back to back memory cells.

5. The method claim 1, wherein forming the first resistive memory cell and the second resistive memory cell includes forming back to back memory cells.

6. The method claim 1, wherein forming the first resistive memory cell and the third resistive memory cell includes forming front to front memory cells.

7. The method of claim 1, including forming different dielectric materials between the first and second resistive memory cells than between the first and third resistive memory cells.

8. The method of claim 1, including forming a number of dielectric materials between the first and second resistive memory cells and a different number of dielectric materials between the first and third resistive memory cells.

9. The method of claim 8, wherein the number of dielectric materials between the first and second resistive memory cells is greater than the different number of dielectric materials between the first and third resistive memory cells.

10. The method of claim 1, wherein forming the first, second, and third resistive memory cells includes forming phase change memory cells, and wherein at least one of the first, second, and third heater elements is formed of a chalcogenide.

11. A method of forming a number of memory cells, the method comprising:

forming a first dielectric material on a first conductive material and a second dielectric material;

forming a number of openings by removing a number of portions of the first dielectric material, wherein each of the number of openings includes angled sidewalls;

forming a heater material in each of the number of openings;

forming a third dielectric material on the heater material;

removing a portion of the third dielectric material and a portion of the heater material in each of the number of openings to form a number of heaters corresponding to a respective number of resistive memory cells;

forming a fourth dielectric material in each of the number of openings;

removing a portion of the first dielectric material, a portion of the heater material, a portion of the third dielectric material, and a portion of the fourth dielectric material to form a planar surface;

forming a resistance variable material on the planar surface; and

forming a conductive cap on the resistance variable material.

12. The method claim 11, wherein the angled sidewalls are at an angle that is less than 90°

with respect to an upper surface of the first conductive material.

13. The method claim 11, wherein the number of heaters are L-shaped heaters having horizontal base portions and vertically angled wall portions.

14. The method claim 11, wherein forming a number of openings by removing a number of portions of the first dielectric material includes using an etch chemistry that includes hydrogen bromide, trifluoromethane, sulfur hexafluoride, and oxygen.

15. The method claim 11, wherein forming the first dielectric material, forming the third dielectric material, and forming the fourth dielectric material forms a number of dielectric interfaces between the number of heaters.

16. An array of memory cells, comprising:

a first resistive memory cell having a first heater element angled with respect to a vertical plane;

a second resistive memory cell adjacent to the first resistive memory cell and having a second heater element angled with respect to the vertical plane and toward the first heater; and

a third resistive memory cell adjacent to the first resistive memory cell and having a third heater element angled with respect to the vertical plane and away from the first heater element.

17. The array of claim 16, wherein a distance between the first heater element and the second heater element is less than a distance between the first heater element and the third heater element.

18. The array of claim 16, wherein the first and second resistive memory cells are front to front memory cells.

19. The array of claim 16, wherein the first and third resistive memory cells are front to front memory cells.

20. The array of claim 16, wherein a first number of dielectric interfaces are between the first heater element and the second heater element and a second number of dielectric interfaces are between the first heater element and the third heater element, the first number of dielectric interfaces being different than the second number of dielectric interfaces.

21. A memory array, comprising:

a number of resistive storage elements;

wherein each of the respective number resistive storage elements include a resistance variable material formed between an L-shaped heater element and a conductive cap material, the L-shaped heater element including a horizontal base portion and an angled vertical wall portion,

wherein at least two adjacent resistive storage elements of the number of resistive storage elements include L-shaped heater elements having their angled vertical wall portions angled towards each other, and

wherein at least two adjacent resistive storage elements of the number of resistive storage elements include L-shaped heater elements having their angled vertical wall portions angled away from each other; and

a select device coupled to each of the respective number of resistive storage elements.

22. The memory array of claim 21, including:

a first number of dielectric interfaces between the at least two adjacent resistive storage elements having angled vertical wall portions angled towards each other; and

a second number of dielectric interfaces between the at least two adjacent resistive storage elements having angled vertical wall portions angled away each other, wherein the first number of dielectric interfaces is different than the second number of dielectric interfaces.

23. The memory array of claim 21, wherein the resistance variable material is a phase change material.

24. The memory array of claim 23, wherein the heater elements are formed of a chalcogenide alloy.

25. The memory array of claim 24, wherein the chalcogenide alloy includes an alloy of germanium, antimony, and tellurium (GST).