Methods of Forming Replacement Gate Structures for Semiconductor Devices
First Claim
1. A method of forming a transistor, comprising:
- forming a sacrificial gate structure above a semiconducting substrate;
removing said sacrificial gate structure to thereby define a gate cavity;
forming a layer of insulating material in said gate cavity;
forming a layer of metal within said gate cavity above said layer of insulating material;
forming a sacrificial material in said gate cavity so as to cover a portion of said layer of metal and thereby define an exposed portion of said layer of metal;
performing an etching process on said exposed portion of said layer of metal to thereby remove said exposed portion of said layer of metal from within said gate cavity;
after performing said etching process, removing said sacrificial material; and
forming a conductive material above the previously covered portion of said layer of metal.
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Accused Products
Abstract
Disclosed herein are methods of forming replacement gate structures. In one example, the method includes forming a sacrificial gate structure above a semiconducting substrate, removing the sacrificial gate structure to thereby define a gate cavity, forming a layer of insulating material in the gate cavity and forming a layer of metal within the gate cavity above the layer of insulating material. The method further includes forming a sacrificial material in the gate cavity so as to cover a portion of the layer of metal and thereby define an exposed portion of the layer of metal, performing an etching process on the exposed portion of the layer of metal to thereby remove the exposed portion of the layer of metal from within the gate cavity, and, after performing the etching process, removing the sacrificial material and forming a conductive material above the remaining portion of the layer of metal.
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Citations
34 Claims
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1. A method of forming a transistor, comprising:
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forming a sacrificial gate structure above a semiconducting substrate; removing said sacrificial gate structure to thereby define a gate cavity; forming a layer of insulating material in said gate cavity; forming a layer of metal within said gate cavity above said layer of insulating material; forming a sacrificial material in said gate cavity so as to cover a portion of said layer of metal and thereby define an exposed portion of said layer of metal; performing an etching process on said exposed portion of said layer of metal to thereby remove said exposed portion of said layer of metal from within said gate cavity; after performing said etching process, removing said sacrificial material; and forming a conductive material above the previously covered portion of said layer of metal. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A method of forming a transistor, comprising:
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forming a sacrificial gate structure above a semiconducting substrate; removing said sacrificial gate structure to thereby define a gate cavity; forming a layer of insulating material in said gate cavity; forming a first layer of metal within said gate cavity above said layer of insulating material; forming a second layer of metal within said gate cavity above said first layer of metal; forming a sacrificial material in said gate cavity so as to cover a portion of said second layer of metal and thereby define an exposed portion of said first layer of metal and said second layer of metal; performing at least one etching process on said exposed portions of said second layer of metal and said first layer of metal to thereby remove said exposed portions of said second layer of metal and said first layer of metal from within said gate cavity; after performing said at least one etching process, removing said sacrificial material; and forming a conductive gate electrode material above said previously covered portions of said first and second layers of metal. - View Dependent Claims (10, 11, 12, 13, 14, 15)
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16. A method of forming first and second transistors, comprising:
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forming a sacrificial gate structure above a semiconducting substrate for each of said first and second transistor; removing said sacrificial gate structures to thereby define a first gate cavity and a second gate cavity for each of said first and second transistors, respectively; forming a layer of insulating material in each of said first and second gate cavities; forming a first layer of metal within in each of said first and second gate cavities above said layer of insulating material; forming a second layer of metal within each of said first and second gate cavities above said first layer of metal; forming a sacrificial material within each of said first and second gate cavities so as to cover a portion of said second layer of metal and thereby define an exposed portion of said first layer of metal and said second layer of metal; performing at least one etching process on said exposed portions of said second layer of metal and said first layer of metal to thereby remove said exposed portions of said second layer of metal and said first layer of metal from within each of said first and second gate cavities; and after performing said at least one etching process, removing said sacrificial material. - View Dependent Claims (17, 18, 19, 20, 21, 22, 23, 24, 25, 26)
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27. A device, comprising:
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a first transistor and a second transistor formed in and above a semiconducting substrate, each of said first and second transistors comprising a gate insulation layer, a first work function adjusting metal layer positioned above the gate insulation layer and a gate electrode positioned above the first work function adjusting metal layer, wherein said gate electrode for each of said first and second transistors has an upper portion with a width at its top that is greater than a width of a lower portion of said gate electrode at its bottom; and a second work function adjusting layer positioned only in said second transistor, said second work function adjusting layer being positioned between said first work function adjusting layer and said gate electrode in said second transistor only, wherein said upper portion of said gate electrode of said first transistor is positioned above and contacts an upper surface of said first work function adjusting layer and also contacts said gate insulation layer, while said upper portion of said gate electrode of said second transistor is positioned above and contacts an upper surface of each of said first and second work function adjusting layers and also contacts said gate insulation layer. - View Dependent Claims (28, 29, 30, 31, 32, 33, 34)
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Specification