SEMICONDUCTOR DEVICE

• US 20130187238A1
• Filed: 06/11/2012
• Published: 07/25/2013
• Est. Priority Date: 01/23/2012
• Status: Active Grant

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Shirai, Koji, Shimizu, Mariko
• Granted Patent: US 8,890,281 B2
• Time in Patent Office: Days
• US Class Current: 257/369
• CPC Class Codes: H01L 27/0629 in combination with diodes, or resistors, or capacitors
• CPC Class Codes: H01L 29/0619 with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
• CPC Class Codes: H01L 29/66106 Zener diodes
• CPC Class Codes: H01L 29/7833 with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/866 Zener diodes

Abstract

According to one embodiment, a semiconductor device includes a first semiconductor layer of a first conductivity type, a second semiconductor layer of a first conductivity type, a third semiconductor layer of a second conductivity type, an isolation layer, and a guard ring layer of the second conductivity type. The second semiconductor layer is provided on the first semiconductor layer. The third semiconductor layer is provided on the second semiconductor layer to be joined to the second semiconductor layer. The isolation layer surrounds a periphery of the third semiconductor layer and is deeper than the third semiconductor layer. The guard ring layer is provided between the third semiconductor layer and the isolation layer, adjacent to the third semiconductor layer, and deeper than the third semiconductor layer.

Claims

1. A semiconductor device comprising:

a first semiconductor layer of a first conductivity type;

a second semiconductor layer of a first conductivity type provided on the first semiconductor layer;

a third semiconductor layer of a second conductivity type provided on the second semiconductor layer to be joined to the second semiconductor layer;

an isolation layer surrounding a periphery of the third semiconductor layer and being deeper than the third semiconductor layer; and

a guard ring layer of the second conductivity type provided between the third semiconductor layer and the isolation layer, being adjacent to the third semiconductor layer, and being deeper than the third semiconductor layer.

2. The device according to claim 1, wherein the guard ring layer continuously surrounds the third semiconductor layer.

3. The device according to claim 1, wherein a second conductivity type impurity concentration of the guard ring layer is lower than a second conductivity type impurity concentration of the third semiconductor layer.

4. The device according to claim 1, wherein the isolation layer is deeper than the second semiconductor layer.

5. The device according to claim 1, wherein the isolation layer includes a trench formed on a top surface side of the device and an insulator buried in the trench.

6. The device according to claim 1, wherein a first conductivity type impurity concentration of the second semiconductor layer is higher than a first conductivity type impurity concentration of the first semiconductor layer.

7. The device according to claim 1, further comprising a fourth semiconductor layer of a first conductivity type provided on the first semiconductor layer on an opposite side of the isolation layer from a region including the third semiconductor layer and the guard ring layer.

8. The device according to claim 7, wherein an impurity concentration of the fourth semiconductor layer is higher than an impurity concentration of the first semiconductor layer.

9. The device according to claim 7, wherein the second semiconductor layer and the fourth semiconductor layer have a same depth and a same impurity concentration.

10. The device according to claim 1, wherein the guard ring layer is provided on an entirety of a side surface of the third semiconductor layer and the side surface of the third semiconductor layer is not in contact with the second semiconductor layer.

11. The device according to claim 1, wherein a P-N junction of the second semiconductor layer and the third semiconductor layer is formed only directly under the third semiconductor layer.

12. The device according to claim 1, wherein an impurity concentration of the second semiconductor layer and an impurity concentration of the third semiconductor layer are 1×

10²⁰ to 1×

10²¹ (cm<sup>−

3</sup>).

13. The device according to claim 1, wherein an impurity concentration of the guard ring layer is 1×

10¹⁸ to 1×

10¹⁹ (cm<sup>−

3</sup>).

14. The device according to claim 1, wherein the first conductivity type is a P type and the second conductivity type is an N type.

15. The device according to claim 1, wherein the device is a Zener diode.

16. The device according to claim 15, wherein breakdown occurs earlier at a P-N junction of the second semiconductor layer and the third semiconductor layer than at a P-N junction of the second semiconductor layer and the guard ring layer.

17. A semiconductor device comprising:

a substrate;

a diode provided on the substrate;

a first transistor provided on the substrate; and

a second transistor provided on the substrate,

the diode including;

a first semiconductor layer of a first conductivity type provided on the substrate;

a second semiconductor layer of the first conductivity type provided on the first semiconductor layer;

a third semiconductor layer of a second conductivity type provided on the second semiconductor layer to be joined to the second semiconductor layer;

an isolation layer surrounding a periphery of the third semiconductor layer and being deeper than the third semiconductor layer; and

a guard ring layer of the second conductivity type provided between the third semiconductor layer and the isolation layer, being adjacent to the third semiconductor layer, and being deeper than the third semiconductor layer,

the first transistor including;

a first conductivity type source layer;

a first conductivity type drain layer;

a second conductivity type channel region provided between the first conductivity type source layer and the first conductivity type drain layer;

a first gate insulating film provided on the second conductivity type channel region; and

a first gate electrode provided on the first gate insulating film,

the second transistor including;

a second conductivity type source layer;

a second conductivity type drain layer;

a first conductivity type channel region provided between the second conductivity type source layer and the second conductivity type drain layer;

a second gate insulating film provided on the first conductivity type channel region; and

a second gate electrode provided on the second gate insulating film.

18. The device according to claim 17, wherein

the second semiconductor layer, the first conductivity type source layer, and the first conductivity type drain layer have a same first conductivity type impurity concentration, and

the third semiconductor layer, the second conductivity type source layer, and the second conductivity type drain layer have a same second conductivity type impurity concentration.

19. The device according to claim 17, wherein the second transistor further includes a second conductivity type semiconductor layer being adjacent to the second conductivity type source layer on a side facing the first conductivity type channel region and to the second conductivity type drain layer on a side facing the first conductivity type channel region and having a same second conductivity type impurity concentration as the guard ring layer of the diode.