PIXEL STRUCTURES AND ELECTRONIC DEVICES COMPRISING THE SAME

• US 20130188108A1
• Filed: 01/18/2013
• Published: 07/25/2013
• Est. Priority Date: 01/20/2012
• Status: Active Grant

• Current Assignee: InnoLux Corporation
• Original Assignee: InnoLux Corporation
• Inventors: WANG, Chung-Yi, WANG, An-Chang, SUNG, Li-Wei, HSIEH, Yao-Lien
• Granted Patent: US 9,274,385 B2
• Time in Patent Office: Days
• US Class Current: 349/42
• CPC Class Codes: G02F 1/134318 having a patterned common electrode
• CPC Class Codes: G02F 1/134336 Matrix
• CPC Class Codes: G02F 1/134345 Subdivided pixels, e.g. for grey scale or redundancy
• CPC Class Codes: G02F 1/136286 Wiring, e.g. gate line, drain line

Abstract

In an embodiment of the disclosure, a pixel structure is provided. The pixel structure includes a first sub-pixel row including a plurality of sub-pixels electrically connecting to a first scan line, and a second sub-pixel row including a plurality of sub-pixels, wherein the first scan line passes through an area of the sub-pixels of the second sub-pixel row.

Claims

1. A pixel structure, comprising:

a first sub-pixel row comprising a plurality of sub-pixels electrically connecting to a first scan line; and

a second sub-pixel row comprising a plurality of sub-pixels, wherein the first scan line passes through an area of the sub-pixels of the second sub-pixel row.

2. The pixel structure as claimed in claim 1, wherein the sub-pixels of the first sub-pixel row and the second sub-pixel row are in a shape of a rectangle, rhombus or polygon.

3. The pixel structure as claimed in claim 1, wherein the sub-pixels of the first sub-pixel row comprise one of red, blue or green sub-pixels or a combination thereof.

4. The pixel structure as claimed in claim 1, wherein the sub-pixels of the second sub-pixel row comprise one of red, blue or green sub-pixels or a combination thereof.

5. The pixel structure as claimed in claim 1, wherein the area of the sub-pixels of the second sub-pixel row where the first scan line passes through, corresponds to a liquid crystal shadow area.

6. The pixel structure as claimed in claim 1, wherein the sub-pixels of the second sub-pixel row are respectively disposed between the sub-pixels of the first sub-pixel row such that the sub-pixels of the first sub-pixel row and the sub-pixels of the second sub-pixel row are in a staggered arrangement.

7. The pixel structure as claimed in claim 1, further comprising a plurality of first data lines passing through an area of the sub-pixels of the first sub-pixel row.

8. The pixel structure as claimed in claim 7, wherein the area of the sub-pixels of the first sub-pixel row where the first data lines pass through, corresponds to a liquid crystal shadow area.

9. The pixel structure as claimed in claim 7, further comprising a plurality of second data lines passing through an area of the sub-pixels of the second sub-pixel row.

10. The pixel structure as claimed in claim 9, wherein the area of the sub-pixels of the second sub-pixel row where the second data lines pass through, corresponds to a liquid crystal shadow area.

11. The pixel structure as claimed in claim 1, further comprising a plurality of common electrodes disposed on the edges of the sub-pixels of the first sub-pixel row and the second sub-pixel row.

12. The pixel structure as claimed in claim 11, wherein the common electrodes are zigzag or concavo-convex.

13. The pixel structure as claimed in claim 7, wherein the first scan line passes through the edges of the sub-pixels of the first sub-pixel row and is vertical to the first data lines.

14. The pixel structure as claimed in claim 1, wherein the first scan line passes through the center of the sub-pixels of the second sub-pixel row.

15. The pixel structure as claimed in claim 9, further comprising a plurality of driving devices, wherein each of the driving devices simultaneously controls one first data line and one second data line.

16. The pixel structure as claimed in claim 1, further comprising a plurality of driving transistors, wherein the driving transistors are electrically connected to the sub-pixels of the first sub-pixel row and disposed between the two adjacent sub-pixels of the second sub-pixel row.

17. An electronic device incorporating a display panel, the display panel comprising:

a first sub-pixel row comprising a plurality of sub-pixels electrically connecting to a first scan line; and

a second sub-pixel row comprising a plurality of sub-pixels, wherein the first scan line passes through an area of the sub-pixels of the second sub-pixel row.