TEMPERATURE COMPENSATION OF CONDUCTIVE BRIDGE MEMORY ARRAYS

• US 20130188431A1
• Filed: 01/20/2012
• Published: 07/25/2013
• Est. Priority Date: 01/20/2012
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk 3D LLC (Western Digital Corporation)
• Inventors: Scheuerlein, Roy E., Samachisa, George
• Granted Patent: US 8,576,651 B2
• Time in Patent Office: Days
• US Class Current: 365/189.09
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 13/0004 comprising amorphous/crystalline phase transition cells
• CPC Class Codes: G11C 13/0011 comprising conductive bridging RAM [CBRAM] or programming metallization cells [PMCs]
• CPC Class Codes: G11C 13/0035 Evaluating degradation, retention or wearout, e.g. by counting writing cycles
• CPC Class Codes: G11C 13/0038 Power supply circuits
• CPC Class Codes: G11C 13/004 Reading or sensing circuits or methods
• CPC Class Codes: G11C 13/0064 Verifying circuits or methods
• CPC Class Codes: G11C 13/0069 Writing or programming circuits or methods
• CPC Class Codes: G11C 16/349 Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles
• CPC Class Codes: G11C 2029/1202 Word line control
• CPC Class Codes: G11C 2029/1204 Bit line control
• CPC Class Codes: G11C 2213/71 Three dimensional array
• CPC Class Codes: G11C 2213/77 Array wherein the memory element being directly connected to the bit lines and word lines without any access device being used
• CPC Class Codes: G11C 29/021 in voltage or current generators
• CPC Class Codes: G11C 29/028 with adaption or trimming of parameters
• CPC Class Codes: G11C 5/02 Disposition of storage elements, e.g. in the form of a matrix array
• CPC Class Codes: G11C 5/063 Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
• CPC Class Codes: G11C 5/14 Power supply arrangements , e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
• CPC Class Codes: G11C 7/00 Arrangements for writing information into, or reading information out from, a digital store G11C5/00 takes precedence; auxiliary circuits for stores using semiconductor devices G11C11/4063, G11C11/413
• CPC Class Codes: G11C 7/04 with means for avoiding disturbances due to temperature effects
• CPC Class Codes: G11C 7/12 : Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
• CPC Class Codes: G11C 8/08 : Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines

Abstract

Methods for operating a semiconductor memory array including dynamically adjusting control line voltages (e.g., unselected word line or unselected bit line voltages) based on one or more array conditions associated with the semiconductor memory array are described. The one or more array conditions may include a temperature associated with the semiconductor memory array or a particular number of write cycles associated with the semiconductor memory array. In some embodiments, an intermediate voltage is generated based on the one or more array conditions and applied to the unselected word lines and the unselected bit lines of the semiconductor memory array. The one or more intermediate voltages may be generated such that a first voltage difference across unselected memory cells sharing a selected word line is different from a second voltage difference across other unselected memory cells sharing a selected bit line based on the one or more array conditions.

Claims

1. A method for operating a non-volatile semiconductor memory array, comprising:

acquiring a temperature associated with the semiconductor memory array, the semiconductor memory array includes a first set of control lines arranged in a first direction and a second set of control lines arranged in a second direction, the first set of control lines includes a first particular control line and a plurality of other first control lines, the second set of control lines includes a second particular control line and a plurality of other second control lines, the semiconductor memory array includes a first semiconductor storage element disposed between the first particular control line and the second particular control line;

applying a selected first control line voltage to the first particular control line;

applying a selected second control line voltage to the second particular control line;

applying one or more unselected first control line voltages based on the temperature to the plurality of other first control lines;

applying one or more unselected second control line voltages based on the temperature to the plurality of other second control lines; and

setting the first semiconductor storage element into a first state in response to the applying a selected first control line voltage and the applying a selected second control line voltage.

2. The method of claim 1, wherein:

the first state is associated with a programming state of the first semiconductor storage element; and

the selected first control line voltage is associated with a programming voltage of the first semiconductor storage element.

3. The method of claim 1, further comprising:

generating the one or more unselected first control line voltages prior to the applying one or more unselected first control line voltages, the generating the one or more unselected first control line voltages includes generating the one or more unselected first control line voltages such that a first voltage difference between the one or more unselected first control line voltages and the selected second control line voltage is less than a second voltage difference between the selected first control line voltage and the one or more unselected second control line voltages.

4. The method of claim 3, further comprising:

determining a particular number of write cycles associated with the semiconductor memory array, the generating the one or more unselected first control line voltages includes generating the one or more unselected first control line voltages such that the first voltage difference between the one or more unselected first control line voltages and the selected second control line voltage is less than the second voltage difference between the selected first control line voltage and the one or more unselected second control line voltages by a particular amount, the particular amount is based on the particular number of write cycles.

5. The method of claim 4, wherein:

the determining a particular number of write cycles includes determining a number of write cycles that have occurred since a last erase of the semiconductor memory array.

6. The method of claim 3, further comprising:

determining a particular number of write cycles associated with a page within the semiconductor memory array, the page is associated with the first particular control line, the generating the one or more unselected first control line voltages includes generating the one or more unselected first control line voltages such that the first voltage difference between the one or more unselected first control line voltages and the selected second control line voltage is less than the second voltage difference between the selected first control line voltage and the one or more unselected second control line voltages by a particular amount, the particular amount is based on the particular number of write cycles

7. The method of claim 6, wherein:

the determining a particular number of write cycles includes determining a number of write cycles that have occurred since a last refresh of the page.

8. The method of claim 3, wherein:

the generating one or more unselected first control line voltages is performed by a voltage generation circuit that generates voltages that are complementary to absolute temperature.

9. The method of claim 1, wherein:

the first state is associated with a reading state of the first semiconductor storage element; and

the selected first control line voltage is associated with a reading voltage of the first semiconductor storage element.

10. The method of claim 1, wherein:

the one or more unselected first control line voltages are greater than the selected second control line voltage and less than the selected first control line voltage; and

the one or more unselected second control line voltages are greater than the selected second control line voltage and less than the selected first control line voltage.

11. The method of claim 1, further comprising:

floating at least a portion of the plurality of other second control lines prior to the applying a selected first control line voltage.

12. The method of claim 1, wherein:

the second set of control lines comprises vertically oriented bit lines.

13. The method of claim 1, wherein:

the first set of control lines comprises word lines; and

the second set of control lines comprises bit lines.

14. The method of claim 1, wherein:

the semiconductor memory array comprises a cross-point memory array.

15. The method of claim 1, wherein:

the first semiconductor storage element comprises a non-volatile storage element.

16. The method of claim 1, wherein:

the first semiconductor storage element includes a conductive bridge memory element.

17. The method of claim 1, wherein:

the first semiconductor storage element includes a memory element in series with a steering element.

18. The method of claim 17, wherein:

the steering element comprises a diode.

19. The method of claim 1, wherein:

the acquiring a temperature associated with the semiconductor memory array includes sensing the temperature using a temperature sensor.

20. A method for operating a non-volatile semiconductor memory array, comprising:

detecting a first condition associated with the semiconductor memory array, the detecting a first condition includes at least one of detecting a particular temperature associated with the semiconductor memory array or detecting a particular number of write cycles associated with the semiconductor memory array, the semiconductor memory array includes a plurality of word lines arranged in a first direction and a plurality of bit lines arranged in a second direction, the plurality of word lines includes a first word line and one or more other word lines, the plurality of bit lines includes a first bit line and one or more other bit lines, the semiconductor memory array includes a first semiconductor storage element disposed between the first word line and the first bit line;

applying a selected word line voltage to the first word line;

applying one or more intermediate voltages based on the first condition to the one or more other word lines and the one or more other bit lines; and

setting the first semiconductor storage element into a first state in response to the applying a selected word line voltage.

21. The method of claim 20, further comprising:

applying a selected bit line voltage to the first bit line; and

generating the one or more intermediate voltages prior to the applying one or more intermediate voltages, the generating the one or more intermediate voltages includes generating the one or more intermediate voltages such that a first voltage difference between the one or more intermediate voltages and the selected bit line voltage is less than a second voltage difference between the selected word line voltage and the one or more intermediate voltages by a particular amount, the particular amount is based on the first condition.

22. The method of claim 21, further comprising:

detecting a second condition associated with the semiconductor memory array subsequent to the detecting a first condition; and

applying one or more second intermediate voltages based on the second condition to the one or more other word lines and the one or more other bit lines, the applying one or more second intermediate voltages is performed subsequent to the applying one or more intermediate voltages, the one or more second intermediate voltages are different from the one or more intermediate voltages.

23. The method of claim 20, wherein:

the detecting a particular number of write cycles includes determining a number of write cycles that have occurred since a last erase of the semiconductor memory array.

24. The method of claim 20, wherein:

the semiconductor memory array includes a page associated with the first word line, the detecting a particular number of write cycles includes determining a number of write cycles that have occurred since a last refresh of the page.

25. The method of claim 20, wherein:

the one or more intermediate voltages are greater than the selected bit line voltage and less than the selected word line voltage.

26. The method of claim 20, wherein:

the first state is associated with a programming state of the first semiconductor storage element; and

the selected word line voltage is associated with a programming voltage of the first semiconductor storage element.

27. The method of claim 21, wherein:

the generating the one or more intermediate voltages is performed by a voltage generation circuit that generates voltages that are dynamically adjusted complementary to absolute temperature changes.

28. The method of claim 20, further comprising:

floating the one or more other bit lines prior to the applying a selected word line voltage.

29. The method of claim 20, wherein:

the plurality of bit lines comprises vertically oriented bit lines.

30. The method of claim 20, wherein:

the first semiconductor storage element comprises a non-volatile storage element.

31. The method of claim 20, wherein:

the first semiconductor storage element includes a conductive bridge memory element.

32. A non-volatile storage system, comprising:

a semiconductor memory array, the semiconductor memory array includes a plurality of word lines arranged in a first direction and a plurality of bit lines arranged in a second direction, the plurality of word lines includes a first word line and one or more other word lines, the plurality of bit lines includes a first bit line and one or more other bit lines, the semiconductor memory array includes a first semiconductor storage element disposed between the first word line and the first bit line;

a first voltage reference circuit, the first voltage reference circuit generates one or more intermediate voltages based on a temperature associated with the semiconductor memory array;

a second voltage reference circuit, the second voltage reference circuit generates a selected word line voltage based on the temperature; and

one or more managing circuits in communication with the plurality of word lines and the plurality of bit lines, the one or more managing circuits bias the one or more other word lines to the one or more intermediate voltages and bias the one or more other bit lines to the one or more intermediate voltages, the one or more managing circuits bias the first word line to the selected word line voltage and bias the first bit line to a selected bit line voltage.

33. The non-volatile storage system of claim 32, wherein:

the first voltage reference circuit generates the one or more intermediate voltages such that a first voltage difference between the one or more intermediate voltages and the selected bit line voltage is less than a second voltage difference between the selected word line voltage and the one or more intermediate voltages by a particular amount, the particular amount is based on the temperature.

34. The non-volatile storage system of claim 32, wherein:

the first voltage reference circuit and the second voltage reference circuit generate voltages that are complementary to absolute temperature.

35. The non-volatile storage system of claim 32, wherein:

the one or more intermediate voltages are greater than the selected bit line voltage and less than the selected word line voltage.

36. The non-volatile storage system of claim 32, wherein:

the plurality of bit lines comprises vertically oriented bit lines; and

the first semiconductor storage element comprises a non-volatile storage element.