MEMORY CONTROL DEVICE, CONTROL METHOD, AND INFORMATION PROCESSING APPARATUS

• US 20130191587A1
• Filed: 01/19/2013
• Published: 07/25/2013
• Est. Priority Date: 01/19/2012
• Status: Abandoned Application

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Renesas Electronics Corporation
• Inventors: TORII, Sunao
• Application Number:
  US13/745,781
• Publication Number:
  US 20130191587A1
• Time in Patent Office: Days
• US Class Current: 711/105
• CPC Class Codes: G06F 12/0811 with multilevel cache hierarchies
• CPC Class Codes: G06F 12/0862 with prefetch
• CPC Class Codes: G06F 12/0884 Parallel mode, e.g. in parallel with main memory or CPU
• CPC Class Codes: G06F 12/0897 with two or more cache hierarchy levels with multilevel cache hierarchies G06F12/0811
• CPC Class Codes: G11C 7/1072 for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories

Abstract

A memory control device includes a first memory, a second memory, a third memory longer in a delay time since start-up until an actual data access, and a control unit. The second memory stores at least a part of data from each data string among multiple data strings with a given number of data as a unit. The third memory stores all of data within the plurality of data strings therein. If a cache miss occurs in the first memory, the control unit conducts hit determination of a cache in the second memory, and starts an access to the third memory. If the result of the hit determination is a cache hit, the control unit reads the part of data falling under the cache hit from the second memory as leading data, reads data other than the part of data, of a data string to which the part of data belongs, from the third memory, and makes a response as subsequent data to the leading data.

Claims

1. A memory control device, comprising:

a first memory that is a cache memory of a given hierarchy;

a second memory that is a cache memory of a lower level hierarchy than that of at least the first memory;

a third memory that is a lower level hierarchy than that of at least the second memory, and longer in delay time since start-up until an actual data access than the first memory and the second memory; and

a control unit that controls input and output of the first memory, the second memory, and the third memory,

wherein the second memory stores at least a part of data from each data string among a plurality of data strings with given number of data as a unit,

wherein the third memory stores all of data within the plurality of data strings therein,

wherein if a cache miss occurs in the first memory, the control unit conducts hit determination of a cache in the second memory, and starts an access to the third memory, and

wherein if the result of the hit determination is a cache hit, the control unit reads the part of data falling under the cache hit from the second memory as leading data, reads data other than the part of data, of a data string to which the part of data belongs, from the third memory, and makes a response as subsequent data to the leading data.

2. The memory control device according to claim 1,

wherein the part of data has the amount of data which is continuously read from the second memory since an access to the third memory starts until first data is read.

3. The memory control device according to claim 1,

wherein the second memory stores the part of data in a larger number of data strings than that when all of the data within each data string is stored.

4. The memory control device according to claim 1,

wherein the third memory reads the data on the basis of a first request for starting an access, and a second request for designating a data position to be read in the access within the data string,

wherein the control unit issues the first request to the third memory together with the hit determination in the second memory,

wherein if the result of the hit determination is the cache hit, the control unit designates data subsequent to the part of data in a data string falling under the cache hit as the data position, and issues the second request to the third memory, and

wherein if the result of the hit determination is the cache miss, the control unit designates all of data strings falling under the cache miss as the data position, and issues the second request to the third memory.

5. The memory control device according to claim 1,

wherein the control unit writes, in response to a request for writing a specific data string, a part of data in the specific data string into the second memory, and writes data other than the part of data in the specific data string into the third memory, and

wherein after writing the data into the third memory, the control unit writes the part of data written into the second memory, into the third memory.

6. The memory control device according to claim 1,

wherein the second memory further stores partial tag information indicative of a data position of the part of data within the data string,

wherein the control unit determines, in response to an access request including designation of a specific data position to be preferentially output within the data string, that the cache hit occurs when the partial tag information corresponds to the designated data position, and

wherein if the result of the hit determination is the cache hit, the control unit reads the part of data corresponding to the partial tag information falling under the cache bit, from the second memory as the leading data.

7. The memory control device according to claim 1,

wherein the control unit conducts the hit determination in response to a second access request received from a second processor core after receiving a first access request from a first processor core, and

wherein if the determination of the hit determination in response to the second access request is the cache hit, the control unit reads the part of data based on the second access request from the second memory to output the read data to the second processor core while reading data from the third memory to output the read data to the first processor core.

8. The memory control device according to claim 1,

wherein the third memory is a DRAM.

9. A memory control method in a memory control device, including:

a first memory that is a cache memory of a given hierarchy;

a second memory that is a cache memory of a lower level hierarchy than that of at least the first memory; and

a third memory that is a lower level hierarchy than that of at least the second memory, longer in delay time since start-up until an actual data access than the first memory and the second memory, and stores all of, data within the plurality of data strings therein, the method comprising;

if a cache miss occurs in the first memory, conducting hit determination of a cache in the second memory;

starting an access to the third memory together with the hit determination; and

if the result of the hit determination is a cache hit, reading the part of data falling under the cache hit from the second memory as leading data, reading data other than the part of data, of a data string to which the part of data belongs, from the third memory, and making a response as subsequent data to the leading data.

10. An information processing apparatus, comprising:

a processor core;

a first memory that is a cache memory of a given hierarchy;

a second memory that is a cache memory of a lower level hierarchy than that of at least the first memory;

a third memory that is a lower level hierarchy than that of at least the second memory, and longer in delay time since start-up until an actual data access than the first memory and the second memory; and

a control unit that controls input and output of the first memory, the second memory, and the third memory,

wherein the second memory stores at least a part of data from each data string among a plurality of data strings with a given number of data as a unit,

wherein the third memory stores all of data within the plurality of data strings therein,

wherein if a cache miss occurs in the first memory, the control unit conducts hit determination of a cache in the second memory, and starts an access to the third memory, and

wherein if the result of the hit determination is a cache hit, the control unit reads the part of data falling under the cache hit from the second memory as leading data, reads data other than the part of data, of a data string to which the part of data belongs, from the third memory, and makes a response as subsequent data to the leading data.

11. A memory control device, comprising:

a first cache memory;

a second cache memory that is a lower level hierarchy of at least the first cache memory; and

an external memory that is a lower level hierarchy of at least the first cache memory,

wherein if a hit determination result of a cache in the second cache memory is a cache hit, the second cache memory and the external memory are memories of the same hierarchy, and

wherein the hit determination result is a cache miss, the external memory is a lower level hierarchy of the second cache memory.

12. A memory control device having three or more memory hierarchies,

wherein if a cache miss occurs in a cache memory of a high level hierarchy, an access request is made to memories of a plurality of hierarchies which are lower level hierarchies than the hierarchy of the cache memory at the same time, and

wherein response data is responsive to the access request in the order of data response.