NOVEL SEMICONDUCTOR DEVICE AND STRUCTURE

• US 20130193488A1
• Filed: 11/21/2012
• Published: 08/01/2013
• Est. Priority Date: 04/14/2009
• Status: Abandoned Application

• Current Assignee: Monolithic 3D, Inc.
• Original Assignee: Monolithic 3D, Inc.
• Inventors: Or-Bach, Zvi, Sekar, Deepak C., Cronquist, Brian
• Application Number:
  US13/683,500
• Publication Number:
  US 20130193488A1
• Time in Patent Office: Days
• US Class Current: 257/202
• CPC Class Codes: H01L 21/26506 in group IV semiconductors
• CPC Class Codes: H01L 21/26513 of electrically active species
• CPC Class Codes: H01L 21/76254 with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
• CPC Class Codes: H01L 21/8221 Three dimensional integrated circuits stacked in different levels
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 2223/5442 comprising non digital, non alphanumeric information, e.g. symbols
• CPC Class Codes: H01L 2223/54426 for alignment
• CPC Class Codes: H01L 2223/54453 for use prior to dicing
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45124 Aluminium (Al) as principal constituent
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2224/80001 by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/544 Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps test patterns for characterising or monitoring manufacturing processes H01L22/00
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 27/0688 : Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 27/08 : including only semiconductor components of a single kind
• CPC Class Codes: H01L 27/11807 : CMOS gate arrays
• CPC Class Codes: H01L 27/11898 : Input and output buffer/driver structures
• CPC Class Codes: H01L 27/1203 : the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00011 : Not relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/01322 : Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/12032 : Schottky diode
• CPC Class Codes: H01L 2924/1301 : Thyristor
• CPC Class Codes: H01L 2924/1305 : Bipolar Junction Transistor [BJT]
• CPC Class Codes: H01L 2924/13062 : Junction field-effect transistor [JFET]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/3011 : Impedance
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding
• CPC Class Codes: H10B 10/00 : Static random access memory [SRAM] devices
• CPC Class Codes: H10B 10/125 : the MOSFET being a thin film transistor [TFT]
• CPC Class Codes: H10B 12/053 : the transistor being at least partially in a trench in the substrate vertical transistor in combination with a capacitor formed in a substrate trench H10B12/0383
• CPC Class Codes: H10B 12/09 : with simultaneous manufacture of the peripheral circuit region and memory cells
• CPC Class Codes: H10B 12/50 : Peripheral circuit region structures
• CPC Class Codes: H10B 20/00 : Read-only memory [ROM] devices

Abstract

A semiconductor device including: a first single crystal layer including first transistors, first alignment mark, and at least one metal layer, said at least one metal layer overlying said first single crystal layer, wherein the at least one metal layer includes copper or aluminum; and a second layer overlying the at least one metal layer; wherein the second layer includes second transistors, the second transistors include mono-crystal, the second transistors include P type transistors and N type transistors, and the second transistors are aligned to the first alignment mark with less than 40 nm alignment error.

Claims

1. A semiconductor device comprising:

a first single crystal layer comprising first transistors, first alignment mark, and at least one metal layer, said at least one metal layer overlying said first single crystal layer,

wherein said at least one metal layer comprises copper or aluminum; and

a second layer overlying said at least one metal layer;

wherein said second layer comprises second transistors,

wherein said second transistors comprise mono-crystal,

wherein said second transistors comprise P type transistors and N type transistors, and

wherein said second transistors are aligned to said first alignment mark with less than 40 nm alignment error.

2. The semiconductor device according to claim 1, wherein said second layer comprises a single crystal layer less than 0.4 micron thick, wherein the contacts to said second transistors are on the other said of said second layer than said at least one metal layer.

3. The semiconductor device according to claim 1, wherein said second layer is transferred using an ion-cut process.

4. The semiconductor device according to claim 1, wherein

said first transistors construct a plurality of first logic circuits, wherein

said second transistors construct a plurality of second logic circuits;

wherein

each logic circuit in said plurality of first logic circuits has at least one first output, wherein

each logic circuit in said plurality of second logic circuits has a second output, and wherein

said plurality of first transistors comprises a plurality of first selectors adapted to selectively replace at least one of said first outputs with at least one of said second outputs.

5. The semiconductor device according to claim 1, wherein said at least one metal layer comprises a second metal layer overlaying a first metal layer, and wherein said first metal layer has a current carrying capacity substantially higher than said second metal layer.

6. The semiconductor device according to claim 1, comprising a shielding structure designed to protect said at least one metal layer from being damaged by optical annealing of said second layer.

7. A semiconductor device comprising:

a first single crystal layer comprising first transistors, first alignment mark, and at least one metal layer, said at least one metal layer overlying said first single crystal layer,

wherein said at least one metal layer comprises copper or aluminum; and

a second layer overlying said at least one metal layer;

wherein said second layer comprises second transistors, said second transistors comprising mono-crystal,

wherein said second layer comprises a plurality of second layer logic circuits comprising said second transistors, and

wherein said second transistors are aligned to said first alignment mark with less than 40 nm alignment error.

8. The semiconductor device according to claim 7, wherein said second layer comprises a single crystal layer less than 0.4 micron thick, wherein the contacts to said second transistors are on the other said of said second layer than said at least one metal layer.

9. The semiconductor device according to claim 7, wherein said second layer is transferred using an ion-cut process.

10. The semiconductor device according to claim 7, wherein

said first transistors construct a plurality of first logic circuits, wherein

each logic circuit in said plurality of first logic circuits has at least one first output, wherein

each logic circuit in said plurality of second layer logic circuits has a second output, and wherein

said plurality of first transistors comprises a plurality of first selectors adapted to selectively replace at least one of said first outputs with at least one of said second outputs.

11. The semiconductor device according to claim 7, wherein said at least one metal layer comprises a second metal layer overlaying a first metal layer, and wherein said first metal layer has a current carrying capacity substantially higher than said second metal layer.

12. The semiconductor device according to claim 7, comprising a shielding structure designed to protect said at least one metal layer from being damaged by optical annealing of said second layer.

13. The semiconductor device according to claim 7, wherein

said second transistors comprise P type transistors and N type transistors.

14. A semiconductor device comprising:

a first single crystal layer comprising first transistors, first alignment mark, and at least one metal layer, said at least one metal layer overlying said first single crystal layer,

wherein said at least one metal layer comprises copper or aluminum; and

a second layer overlying said at least one metal layer;

wherein said second layer comprises second transistors, said second transistors comprise mono-crystal,

wherein said second layer comprises a plurality of Flip-Flops,

wherein said plurality of Flip-Flops comprises said second transistors, and

wherein said second transistors are aligned to said first alignment mark with less than 40 nm alignment error.

15. The semiconductor device according to claim 14, wherein said second layer comprises a single crystal layer less than 0.4 micron thick, wherein the contacts to said second transistors are on the other said of said second layer than said at least one metal layer.

16. The semiconductor device according to claim 14, wherein said second layer is transferred using an ion-cut process.

17. The semiconductor device according to claim 14, wherein

said first transistors construct a plurality of first logic circuits, wherein

said second transistors construct a plurality of second logic circuits;

wherein

each logic circuit in said plurality of first logic circuits has at least one first output, wherein

each logic circuit in said plurality of second logic circuits has a second output, and wherein

said plurality of first transistors comprises a plurality of first selectors adapted to selectively replace at least one of said first outputs with at least one of said second outputs.

18. The semiconductor device according to claim 14, wherein said at least one metal layer comprises a second metal layer overlaying a first metal layer, and wherein said first metal layer has current a carrying capacity substantially higher than said second metal layer.

19. The semiconductor device according to claim 14, comprising a shielding structure designed to protect said at least one metal layer from being damaged by optical annealing of said second layer.

20. The semiconductor device according to claim 14, wherein

said second transistors comprise P type transistors and N type transistors.