SOI LATERAL MOSFET DEVICES

• US 20130193509A1
• Filed: 08/10/2010
• Published: 08/01/2013
• Est. Priority Date: 05/17/2010
• Status: Active Grant

• Current Assignee: University of Electronic Science and Technology of China
• Original Assignee: University of Electronic Science and Technology of China
• Inventors: Udrea, Florin, Luo, Xiaorong
• Granted Patent: US 8,716,794 B2
• Time in Patent Office: Days
• US Class Current: 257/330
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 29/0619 with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/7809 having both source and drain contacts on the same surface, i.e. Up-Drain VDMOS transistors
• CPC Class Codes: H01L 29/7812 with a substrate comprising an insulating layer, e.g. SOI-VDMOS transistors
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

The present invention relates to a semiconductor power device and power integrated circuits (ICs). The lateral SOI MOSFET in the present comprises a trench gate extended to the dielectric buried layer, one or multiple dielectric trenches in the drift region, and a buried gate in said dielectric trench. The permittivity of the dielectric in said dielectric trench is lower than that of said active layer. Firstly, said dielectric trench not only greatly improves breakdown voltage, but also reduces pitch size. Secondly, the trench gate widens the effective conductive region in the vertical direction. Thirdly, dual gates of said trench gate and buried gate increase channel and current densities. Thereby, specific on-resistance and the power loss are reduced. The device of the present invention has many advantages, such as high voltage, high speed, low power loss, low cost and ease of integration. The device in the present invention is particularly suitable for power integrated circuits and RF power integrated circuits.

Claims

1. An SOI lateral MOSFET device comprising

a semiconductor substrate layer,

a dielectric buried layer,on said semiconductor substrate layer,

an active layer on said dielectric buried layer,

a trench gate in said active layer, consisting of gate dielectric and conductive material surrounded by the gate dielectric, wherein the terminal of said conductive material is trench gate electrode,

wherein, the trench gate going through the active layer to said dielectric buried layer, a drain region and a body region separating from each other on said active layer surface on a side of said trench gate, and drain electrode acting as the drain region terminal,

source region a, body contact region and source region b on the surface of said body region in sequence, with a source electrode as their common terminal,

said body region and source region a is in contact with said trench gate,

a dielectric trench located between said source region b and said drain region, being in contact with said body region and source region b, wherein the permittivity of the dielectric in said dielectric trench is lower than that of the material of said active layer, the depth of the said dielectric trench is larger than that of the body region and less than the thickness of the active layer,

a buried gate of conductive material inset in said dielectric trench in the vicinity of the source region b and surrounded by the dielectric in said dielectric trench, with a depth no less than that of said body region and less than that of dielectric trench, the terminal of said buried gate is the buried gate electrode,

said trench gate electrode and buried gate electrode are connected electrically, and the common terminal of said trench gate electrode and buried gate electrode is a gate electrode.

2. The lateral SOI MOSFET device according to claim 1,

wherein said the lateral SOI MOSFET device is a symmetrical structure, the drain region is in the center of the device, and the dielectric trench, source region b, body contact region, source region a and the trench gate are arranged in sequence outward from said drain region, with the trench gate in the periphery of the device.

3. The lateral SOI MOSFET device according to claim 2,

wherein the lateral SOI MOSFET device is a plane symmetry structure, and the symmetry plane is the plane which divides the drain region into two equal parts and does not go through the said dielectric trench and trench gate.

4. The lateral SOI MOSFET device according to claim 2,

wherein the lateral SOI MOSFET device is an axi-symmetry structure, and the center axis of said drain region is the axis of symmetry.

5. The lateral SOI MOSFET device according to claim 1, wherein the upper portion of the gate dielectric is thinner than the lower portion of the gate dielectric.

6. The lateral SOI MOSFET device according to claim 1, wherein there are n dielectric trenches separating from each other, where n≧

2 and said buried gate is located in the dielectric trench in contact with the body region.

7. The lateral SOI MOSFET device according to claim 6,

wherein the conductivity type of a part of the active layer between dielectric trenches is the same as or different from that of other part of said active layer.

8. The lateral SOI MOSFET device according to claim 6,

wherein the vertical depth and horizontal width of each dielectric trench, and space between two adjacent dielectric trenches are equal or not equal.

9. The lateral SOI MOSFET device according to claim 6,

wherein the dielectric trench in the middle is deeper than the dielectric trenches on both sides when n>

3.

10. The lateral SOI MOSFET device according to claim 1,

wherein said drain region is in contact with said dielectric trench or not.

11. The lateral SOI MOSFET device according to claim 1,

wherein said lateral SOI MOSFET device act as an active device used in integrated circuits (ICs).

12. The lateral SOI MOSFET device according to claim 11, wherein said ICs is Power ICs or RF power ICs.

13. The lateral SOI MOSFET device according to claim 1,

wherein the material of said active layer includes but does not restrict to Si, SiC, SiGe, GaAs or GaN.

14. The lateral SOI MOSFET device according to claim 13,

wherein said active layer is Si material and the dielectric in said dielectric trench is SiO₂ or the dielectric with a lower permittivity than that of SiO₂ and with a higher critical electric field than three times of Si, and

said dielectric includes but does not restrict to SiOF, Carbon doped Oxide (CDO) or SiCOF.

15. The lateral SOI MOSFET device according to claim 13,

wherein said active layer is Si material and gate dielectric is SiO₂ or the dielectric with a higher permittivity than that of SiO₂ and said gate dielectric includes but does not restrict to Si₃N₄, Al₂O₃, ALN or HfO₂.

16. The lateral SOI MOSFET device according to claim 13,

wherein said active layer is Si material and said dielectric buried layer is SiO₂ or the dielectric with a lower permittivity than that of SiO₂ and a higher critical electric field than three times of Si, and said dielectric buried layer includes but does not restrict to SiOF, Carbon doped Oxide (CDO) or SiCOF.

17. The lateral SOI MOSFET device according to claim 6,

wherein said drain region is in contact with said dielectric trench or not.

18. The lateral SOI MOSFET device according to claim 6,

wherein said lateral SOI MOSFET device act as an active device used in integrated circuits (ICs).

19. The lateral SOI MOSFET device according to claim 18,

wherein said ICs is Power ICs or RF power ICs.