SYSTEM AND METHOD FOR GENERATING A CLOCK GATING NETWORK FOR LOGIC CIRCUITS
First Claim
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1. A method for generating a clock gating network for a Very Large Scale Integration (VLSI) system, said method comprising:
- obtaining toggling probabilities of a plurality of flip-flops of the system;
clustering sets of correlated flip-flops having correlated toggling behavior; and
providing a common gater for each cluster of correlated flip-flops.
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Abstract
A system and method for generating a power efficient clock gating network for a Very Large Scale Integration (VLSI) circuit. Statistical analysis is performed upon the activity of component registers of the circuit and registers having correlated toggling behavior are clustered into sets and provided with common clock gaters. The clock gating network may be generated independently from the logical structure of the circuit.
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Citations
16 Claims
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1. A method for generating a clock gating network for a Very Large Scale Integration (VLSI) system, said method comprising:
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obtaining toggling probabilities of a plurality of flip-flops of the system; clustering sets of correlated flip-flops having correlated toggling behavior; and providing a common gater for each cluster of correlated flip-flops. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A method for generating a clock gating network for a logic system comprising a plurality of registers, said method comprising:
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obtaining a hardware description of the logic system; executing a simulation with a representative test bench of the logic system; performing statistical analysis of behavior of the plurality of registers; clustering sets of statistically correlated registers; and providing a common gater for each cluster of correlated registers. - View Dependent Claims (11, 12, 13, 14, 15, 16)
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10. A clock gating network for a Very Large Scale Integration (VLSI) circuit, said network comprising a plurality of clusters of correlated registers said correlated registers having statistically correlated toggling behavior, wherein each cluster of correlated registers is gated by a common gater.
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