CURRENT-BALANCING IN INTERLEAVED CIRCUIT PHASES

• US 20130194848A1
• Filed: 01/31/2012
• Published: 08/01/2013
• Est. Priority Date: 01/31/2012
• Status: Active Grant

• Current Assignee: Analog Devices, Inc.
• Original Assignee: Analog Devices, Inc.
• Inventors: Soldano, Marco, Bernardinis, Gabriele
• Granted Patent: US 9,077,243 B2
• Time in Patent Office: Days
• US Class Current: 363/126
• CPC Class Codes: H02M 1/0003 Details of control, feedback or regulation circuits
• CPC Class Codes: H02M 1/0009 Devices or circuits for detecting current in a converter
• CPC Class Codes: H02M 1/4225 using a non-isolated boost converter
• CPC Class Codes: H02M 3/1584 with a plurality of power processing stages connected in parallel
• CPC Class Codes: H02M 3/1586 switched with a phase shift, i.e. interleaved
• CPC Class Codes: Y02B 70/10 Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
• CPC Class Codes: Y02P 80/10 Efficient use of energy, e.g. using compressed air or pressurized fluid as energy carrier

Abstract

A method for balancing an electrical parameter (e.g, a current or a voltage) between phases in a multi-phase interleaved circuit includes sensing the electrical parameter, demultiplexing the electrical parameter in accordance with a phase-select signal, sampling the demultiplexed components into a plurality of digital signals, generating an error signal based on a difference between the digital signals, and modulating the phase-select signal, as applied to the phases, in accordance with the error signal.

Claims

1. A method for balancing phases in a multi-phase interleaved circuit, the method comprising:

sensing an electrical parameter common to the phases;

demultiplexing the electrical parameter in accordance with a phase-select signal;

sampling the demultiplexed components into a plurality of digital signals;

generating an error signal based on a difference between the digital signals; and

modulating the phase-select signal, as applied to the phases, in accordance with the error signal.

2. The method of claim 1, wherein the electrical parameter is a current or a voltage.

3. The method of claim 1, wherein generating the error signal comprises integrating the difference between the digital signals.

4. The method of claim 2, wherein generating the error signal comprises applying a scaling factor to a result of the integration.

5. The method of claim 4, further comprising applying a first scaling factor when a duty cycle of the phase-select signal is less than 50% and applying a second scaling factor when the duty cycle of the phase-select signal is greater than 50%.

6. The method of claim 1, wherein sensing the electrical parameter comprises sensing a voltage across a resistor.

7. The method of claim 1, wherein demultiplexing the electrical parameter comprises dividing the electrical parameter into two 180 degree sections.

8. The method of claim 1, wherein modulating the phase select signal comprises modifying the phase-select signal in only one phase.

9. The method of claim 1, wherein modulating the phase select signal comprises modifying the phase-select signal in more than one phase.

10. A system for balancing phases in a multi-phase interleaved circuit, the system comprising:

a demultiplexer for dividing an input signal into a plurality of demultiplexed signals in accordance with a phase-select signal, the input signal being an electrical parameter common to the phases;

an analog-to-digital converter circuit for dividing the demultiplexed signals into a plurality of digital signals;

a comparator for detecting a difference between the plurality of digital signals; and

a modulator for modulating the phase-select signal in accordance with an error signal based at least in part on the detected difference.

11. The method of claim 10, wherein the electrical parameter is a current or a voltage.

12. The system of claim 10, further comprising an integrator for integrating the detected difference prior to its use by the modulator.

13. The system of claim 10, further comprising a scaler for applying a scaling factor to a result of the integration prior to its use by the modulator.

14. The system of claim 10, wherein the analog-to-digital converter circuit comprises a plurality of analog-to-digital converters.

15. The system of claim 14, wherein each analog-to-digital converter comprises a sigma-delta analog-to-digital converter.

16. The system of claim 10, wherein the phases comprise two phases.

17. The system of claim 10, wherein the multi-phase interleaved circuit comprises a multi-phase power-factor correction circuit.