MEMORY MANAGEMENT DEVICE AND MEMORY MANAGEMENT METHOD

• US 20130198437A1
• Filed: 07/27/2012
• Published: 08/01/2013
• Est. Priority Date: 01/27/2010
• Status: Abandoned Application

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Atsushi Kunimatsu, Hiroto Nakai, Hiroyuki Sakamoto, Masaki Miyagawa, Reina Nishino, Takashi Omizo, Tsutomu Owa
• Inventors: OWA, Tsutomu, KUNIMATSU, Atsushi, NAKAI, Hiroto, MIYAGAWA, Masaki, NISHINO, Reina, SAKAMOTO, Hiroyuki, OMIZO, Takashi
• Application Number:
  US13/560,206
• Publication Number:
  US 20130198437A1
• Time in Patent Office: Days
• US Class Current: 711/103
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 12/0804 with main memory updating G06F12/0806 takes precedence
• CPC Class Codes: G06F 2212/202 Non-volatile memory
• CPC Class Codes: G06F 2212/7202 Allocation control and policies
• CPC Class Codes: G06F 2212/7203 Temporary buffering, e.g. using volatile buffer or dedicated buffer blocks

Abstract

In an embodiment, a device includes a first unit, a second unit, and a third unit. The first unit generates a write address representing a write position to sequentially store sequential data from a processor to a nonvolatile main memory. The second unit generates order information representing a degree of newness of write. The third unit writes sequentially writes the sequential data at the write address with the order information.

Claims

1. A memory management device comprising:

a determination unit that, when data to be written from a processor to a nonvolatile semiconductor memory generates, determines whether the data is sequential data to be sequentially accessed or normal data that is not the sequential data;

an address generation unit that, when the determination unit determines that the data is the normal data, generates a first write address not to make a write position of the normal data overlap a position indicated by a generated address, and, when the determination unit determines that the data is the sequential data, generates a second write address representing a write position to sequentially store the sequential data;

an order generation unit that generates order information representing a degree of newness of write that occurs; and

a write control unit that, when the address generation unit generates the first write address, writes the normal data at the first write address in correspondence with the order information generated by the order generation unit, and when the address generation unit generates the second write address, sequentially writes the sequential data at the second write address.

2. The memory management device according to claim 1, wherein the address generation unit generates the second write address to store a start of the sequential data at a start of at least one block area to store the sequential data.

3. The memory management device according to claim 1, further comprising a memory management unit that manages a logical address and a physical address for the sequential data and a flag representing that the data is the sequential data in association with each other.

4. The memory management device according to claim 3, wherein the memory management unit further manages the logical address and the physical address for the sequential data and a continuous count of the sequential data in association with each other.

5. The memory management device according to claim 1, wherein the write control unit writes the sequential data to the nonvolatile semiconductor memory in association with a flag representing that the data is the sequential data.

6. The memory management device according to claim 1, wherein the address generation unit sequentially generates an address when write of the normal data from the processor to the nonvolatile semiconductor memory occurs, the address generation unit selects the generated address as the first write address when the generated address is unused, and the address generation unit performs address generation again from an initial value when the generated address reaches a predetermined value.

7. The memory management device according to claim 1, wherein

the write control unit writes status information generated by a status information generation unit in the processor to the nonvolatile semiconductor memory in correspondence with the order information generated by the order generation unit, and

the memory management device further comprises a restoration unit that, when restoring the processor, reads out latest status information from the nonvolatile semiconductor memory based on the order information and restore the processor using the latest status information.

8. The memory management device according to claim 7, wherein the restoration unit is implemented by causing the processor to execute a program stored in the nonvolatile semiconductor memory.

9. The memory management device according to claim 1, wherein

the write control unit writes memory management information managed by a memory management unit to the nonvolatile semiconductor memory in correspondence with the order information generated by the order generation unit, and

the memory management device further comprises a restoration unit that, when restoring the processor, reads out latest memory management information from the nonvolatile semiconductor memory based on the order information and restore the processor using the latest memory management information.

10. The memory management device according to claim 1, wherein

the write control unit manages write count information concerning an area of the nonvolatile semiconductor memory, and

the memory management device further comprises a write count check unit that prohibits write to an area where a write count represented by the write count information exceeds a threshold.

11. The memory management device according to claim 1, further comprising an abnormality detection unit that detects an error in the nonvolatile semiconductor memory, corrects the error when error correction is possible, and prohibits write to an area where the error occurs when error correction is impossible.

12. The memory management device according to claim 1, wherein

the nonvolatile semiconductor memory includes a plurality of types of areas, and

the address generation unit selects an area corresponding to a type of the data from the plurality of types of areas of the nonvolatile semiconductor memory and selects a write address in the selected area.

13. The memory management device according to claim 1, further comprising:

a detection unit that detects performance deterioration in access from the processor to the nonvolatile semiconductor memory; and

a performance deterioration suppressing unit that executes garbage collection processing when the detection unit detects performance deterioration.

14. The memory management device according to claim 1, wherein

the memory management device manages access to a hybrid memory including the nonvolatile semiconductor memory and another semiconductor memory of a type different from the nonvolatile semiconductor memory, and

the address generation unit selects a storage destination memory out of the nonvolatile semiconductor memory and the other semiconductor memory included in the hybrid memory such that one of an access count and an access frequency to a first memory having high reliability or durability exceeds a corresponding one of an access count and an access frequency to a second memory having low reliability or durability.

15. A memory management method comprising:

determining, when data to be written from a processor to a nonvolatile semiconductor memory generates, whether the data is sequential data to be sequentially accessed or normal data that is not the sequential data, by a memory management device;

generating, upon determining that the data is the normal data, a first write address not to make a write position of the normal data overlap a position indicated by a generated address, and generating, upon determining that the data is the sequential data, second write address representing a write position to sequentially store the sequential data, by the memory management device;

generating order information representing a degree of newness of write that occurs, by the memory management device; and

writing, when the first write address generates, the normal data at the first write address in correspondence with the generated order information, and sequentially writing, when the second write address has been generated, the sequential data at the second write address, by the memory management device.

16. The memory management method according to claim 15, wherein the generating the second write address comprises generating the second write address to store a start of the sequential data at a start of at least one block area to store the sequential data.

17. The memory management method according to claim 15, further comprising, by the memory management device, managing a logical address and a physical address for the sequential data and a flag representing that the data is the sequential data in association with each other.

18. The memory management method according to claim 17, further comprising, by the memory management device, managing the logical address and the physical address for the sequential data and a continuous count of the sequential data in association with each other.

19. The memory management method according to claim 15, wherein when writing the sequential data to the nonvolatile semiconductor memory, the sequential data is written in association with a flag representing that the data is the sequential data.

20. The memory management method according to claim 15, wherein the generating the first write address comprises sequentially generating an address when write of the normal data from the processor to the nonvolatile semiconductor memory occurs, selecting the generated address as the first write address when the generated address is unused, and performing address generation again from an initial value when the generated address reaches a predetermined value.