NON-VOLATILE STORAGE

• US 20130198439A1
• Filed: 01/18/2013
• Published: 08/01/2013
• Est. Priority Date: 01/26/2012
• Status: Active Grant

• Current Assignee: Hitachi, Ltd.
• Original Assignee: Hitachi, Ltd.
• Inventors: KUROTSUCHI, Kenzo, MIURA, Seiji
• Granted Patent: US 9,378,131 B2
• Time in Patent Office: Days
• US Class Current: 711/103
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 12/08 in hierarchically structured memory systems, e.g. virtual memory systems
• CPC Class Codes: G06F 12/0802 Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
• CPC Class Codes: G06F 12/1009 using page tables, e.g. page table structures
• CPC Class Codes: G06F 2212/7201 Logical to physical mapping or translation of blocks or pages

Abstract

The non-volatile storage SSD has non-volatile NVM, RAM capable of being accessed at a higher speed than this NVM, and a control unit for controlling accesses to the NVM and to the RAM. The control unit stores in the NVM an address translation table (LPT) that translates a logical address given to access this NVM to a physical address after dividing it into multiple tables, and stores in the RAM the multiple address translation tables-sub on RAM (LPT-SRs) that have been divided into multiple tables.

Claims

1. A non-volatile storage comprising:

first memory of non-volatile type;

second memory capable of being accessed faster than the first memory; and

a control unit for controlling accesses to the first memory and to the second memory,

wherein the control unit stores in the first memory an address translation table for translating a logical address given in order to access the first memory to a physical address with the table being divided into a plurality of partial address translation tables, and stores in the second memory more than one partial address translation tables of the partial address translation tables that were obtained by dividing the table.

2. The non-volatile storage according to claim 1,

wherein the first memory is NAND type flash memory.

3. The non-volatile storage according to claim 1,

wherein the control unit cache-controls the partial address translation tables stored in the second memory.

4. The non-volatile storage according to claim 3,

wherein entries to be searched based on the logical address are limited as the method of cache control.

5. The non-volatile storage according to claim 3,

wherein a cache that is to be discarded is determined based on an access frequency as the method of cache control.

6. The non-volatile storage according to claim 3,

wherein a data size when the partial address translation table updated in the cache control is written back to the first memory is larger than the partial address translation table.

7. The non-volatile storage according to claim 1,

wherein the first memory is phase change memory.

8. The non-volatile storage according to claim 1,

wherein a single semiconductor chip has the first memory and the second memory.

9. The non-volatile storage according to claim 1,

wherein the second memory is phase change memory.

10. A non-volatile storage, comprising:

first memory of non-volatile type;

second memory capable of being accessed faster than the first memory; and

a control unit for controlling accesses to the first memory and to the second memory;

wherein the control unit stores in the first memory a first table for translating a logical address of data of the first memory to a physical address,

stores in the second memory a cache of the first table and a second table for showing where in the first memory the first table is stored, and

stores in the second table a plurality of addresses of the first table in the first memory.

11. In The non-volatile storage according to claim 10,

wherein the second memory is DRAM.

12. The non-volatile storage according to claim 10,

wherein the control unit performs wear leveling of the first table using the second table.

13. The non-volatile storage according to claim 13, comprising:

first memory of non-volatile type;

second memory capable of being accessed faster than the first memory; and

a control unit for controlling accesses to the first memory and to the second memory;

wherein the control unit stores in the first memory an erase table for showing whether the data stored in the first memory is erasable with the table being divided into a plurality of partial erase tables, and

stores in the second memory more than one partial erase tables of the partial erase tables that were obtained by dividing the table.

14. The non-volatile storage according to claim 13,

wherein the control unit stores in the first memory simultaneously the partial erase tables stored in the second memory simultaneously.

15. The non-volatile storage according to claim 13,

wherein the partial erase tables stored in the second memory contain information that makes it possible to find out whether there is a possibility that the divided areas in the first memory may be accessed from the host device.