Enhanced Buffer-Batch management for Energy Efficient Networking

• US 20130198538A1
• Filed: 01/31/2012
• Published: 08/01/2013
• Est. Priority Date: 01/31/2012
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Diab, Wael William, Lindsay, Steven B.
• Granted Patent: US 9,110,668 B2
• Time in Patent Office: Days
• US Class Current: 713/310
• CPC Class Codes: G06F 1/3278 Power saving in modem or I/O interface
• CPC Class Codes: H04L 12/12 Arrangements for remote connection or disconnection of substations or of equipment thereof
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management
• CPC Class Codes: Y02D 30/50 in wire-line communication networks, e.g. low power modes or reduced link rate

Abstract

Various methods and systems are provided for buffer-batch management for energy efficient networking. In one embodiment, among others, a system includes a host device including an interface with a network. A device driver monitors requests to transmit packets from the host device to the network, buffers the packets in memory of the host device when the host device network interface is estimated to be in a low power mode, and initiates transition of the host device network interface to a full power mode based at least in part upon predefined criteria associated with the buffered packets. The host device network interface may begin transmission of the buffered packets when the host device network interface enters the full power mode. The host device network interface may be a network interface controller such as, e.g., an Ethernet controller configured for Energy Efficient Ethernet operation.

Claims

1. A system, comprising:

a host device including an interface with a network; and

a device driver executable by the host device, the device driver including;

logic that monitors host device requests to transmit packets from the host device to the network;

logic that buffers the packets in memory of the host device when the host device network interface is estimated to be in a low power mode; and

logic that initiates transition of the host device network interface to a full power mode based at least in part upon predefined criteria associated with the buffered packets;

where transmission of the buffered packets to the network begins when the host device network interface enters the full power mode.

2. The system of claim 1, wherein the host device network interface is a network interface controller (NIC).

3. The system of claim 2, wherein the NIC is considered to be in the low power mode when a peripheral component interconnect express (PCIE) core of the NIC is estimated to be operating in low power state.

4. The system of claim 3, wherein the NIC is considered to be in the low power mode when both the PCIE core and a physical layer (PHY) core of the NIC are estimated to be operating in low power states.

5. The system of claim 3, wherein the NIC enters the full power mode when both the PCIE core and the PHY core are operating in full power states.

6. The system of claim 2, wherein the NIC is considered to be in the low power mode when a physical layer (PHY) core of the NIC is estimated to be operating in low power state.

7. The system of claim 1, wherein the transition of the host device network interface to the full power mode is initiated when a predefined number of host device requests to transmit packets have been detected after the estimated entry of the NIC in the low power state.

8. The system of claim 1, wherein the transition of the NIC to the full power mode is initiated when a predefined time period expires, where the predefined time period begins when the NIC is estimated to have entered the low power mode.

10. The system of claim 8, wherein the NIC is considered to be in a low power mode when a peripheral component interconnect express (PCIE) core of the NIC is estimated to be operating in a low power state.

11. The system of claim 10, wherein the device driver initiates transfer of the buffered packets to the NIC for transmission when the PCIE core is operating in a full power state.

9. A system, comprising:

a host device including a network interface controller (NIC); and

a device driver executable by the host device, the device driver including;

logic that monitors host device requests to transmit packets from the host device to a network through the NIC;

logic that buffers the packets in memory of the host device when the NIC is estimated to be in a low power mode; and

logic that initiates transition of the NIC to a full power mode based at least in part upon predefined criteria associated with the buffered packets;

where the NIC begins transmission of the buffered packets to the NIC when the NIC enters the full power mode.

12. The system of claim 9, wherein the transition of the NIC to the full power mode is initiated when a predefined number of host device requests to transmit packets have been detected after the NIC entered the low power state.

13. The system of claim 9, wherein the transition of the NIC to the full power mode is initiated when a predefined time period expires, where the predefined time period begins when the NIC enters the low power mode.

14. The system of claim 9, wherein the transition of the NIC to the full power mode is initiated when a predefined time period expires, where the predefined time period begins when a first host device request to transmit packets after the NIC enters the low power mode is detected.

15. The system of claim 9, wherein the transition of the NIC to the full power mode is initiated when a priority level associated with a detected host device request meets a predefined priority criterion.

16. The system of claim 9, wherein the device driver further includes:

logic that monitors the NIC for indications of a packet being received from the network when the NIC is in the low power mode; and

logic that initiates transition of the NIC from the low power mode to the full power mode in response to an indication that a packet is being received.

17. The system of claim 16, wherein the transition of the NIC to the full power mode is initiated if at least one packet has been buffered in the memory of the host device and is not initiated otherwise.

18. The system of claim 9, wherein the NIC is an Ethernet controller configured for Energy Efficient Ethernet (EEE) operation.

19. The system of claim 9, wherein all of the buffered packets are transmitted to the network by the NIC before initiating transition of the NIC to the low power mode.

20. A method, comprising:

estimating a power state of a peripheral component interconnect express (PCIE) core and a physical layer (PHY) core of a network interface controller (NIC);

buffering, in memory external to the NIC, one or more packets for transmission to a network when the PCIE core is estimated as operating in a low power state;

initiating transition of the PCIE core and the PHY core to full power states based at least in part upon predefined criteria associated with the one or more buffered packets; and

initiating transfer of the one or more buffered packets to the NIC for transmission when the PCIE core reaches the full power state.

21. The method of claim 20, further comprising monitoring requests to transmit the one or more packets to the network through the NIC.

22. The method of claim 21, further comprising:

determining a priority level associated with a request to transmit a packet; and

initiating transition of the PCIE core and the PHY core to full power states based at least in part upon the priority level.

23. The method of claim 22, wherein the packet associated with the request to transmit is buffered prior to initiating the transition of the PCIE core and the PHY core.

24. The method of claim 20, further comprising:

initiating transition of the PCIE core to the full power state in response to an indication that the PHY core is transitioning from the low power state to the full power state.

25. The method of claim 24, wherein the PHY core is transitioning to the full power state to receive a packet from the network.

26. The method of claim 20, wherein transition of the PCIE core and the PHY core to the full power states is initiated when a predefined number of packets have been buffered.

27. The method of claim 20, wherein transition of the PCIE core and the PHY core to the full power states is initiated when both the PCIE core and the PHY core have operated in the low power states for a predefined period of time.

28. The method of claim 27, wherein the predefined period of time is based upon a user defined level of packet transmission latency.