Multi-Gate Field Effect Transistor with A Tapered Gate Profile

• US 20130198695A1
• Filed: 10/04/2012
• Published: 08/01/2013
• Est. Priority Date: 02/01/2012
• Status: Abandoned Application

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: International Business Machines Corporation
• Inventors: Bryant, Andres, Chang, Josephine B., Haensch, Wilfried, Leobandung, Effendi, Lin, Chung-Hsun
• Application Number:
  US13/644,398
• Publication Number:
  US 20130198695A1
• Time in Patent Office: Days
• US Class Current: 716/50
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

A multi-gate field effect transistor apparatus and method for making same. The apparatus includes a source terminal, a drain terminal, and a gate terminal which includes a tapered-gate profile. A method for designing a multi-gate field effect transistor includes arranging a source terminal, a drain terminal and a gate terminal with a tapered-gate profile to create a wider gate width on a bottom of a fin.

Claims

1. A method for designing a nonplanar multi-gate fin field effect transistor (FinFET), comprising:

arranging a source terminal, a drain terminal and a gate terminal with a tapered-gate profile along each FinFET sidewall gate to create a wider gate width on a bottom of a fin.

2. The method of claim 1, wherein the apparatus is implemented on a silicon on insulator (SOI) substrate or a bulk substrate.

3. The method of claim 1, further comprising incorporating a hardmask into the multi-gate field effect transistor.

4. The method of claim 3, wherein the gate terminal wraps around the hardmask.

5. The method of claim 3, wherein hardmask has a thickness ranging from approximately 0.5 nanometers to approximately 3 nanometers.

6. The method of claim 3, wherein hardmask has a thickness ranging from approximately 20 nanometers to approximately 30 nanometers.

7. The method of claim 1, further comprising arranging a doping profile flush with the tapered-gate profile.

8. The method of claim 1, further comprising arranging a doping profile overlapping the tapered-gate profile.

9. The method of claim 1, further comprising arranging the tapered-gate profile overlapping a doping profile.

10. The method of claim 1, wherein arranging a source terminal, a drain terminal and a gate terminal with a tapered-gate profile to create a wider gate width on a bottom of a fin provides longer gate length in a bottom portion of a fin to lessen short channel effect penalty.

11. The method of claim 1, wherein the tapered-gate profile includes an angle of the tapered-gate ranging from approximately zero degrees to approximately 90 degrees.