SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE

• US 20130200375A1
• Filed: 01/31/2013
• Published: 08/08/2013
• Est. Priority Date: 02/08/2012
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Yamazaki, Shunpei
• Granted Patent: US 9,859,114 B2
• Time in Patent Office: Days
• US Class Current: 257/57
• CPC Class Codes: H01L 21/02244 of a metallic layer
• CPC Class Codes: H01L 21/02252 formation by plasma treatment, e.g. plasma oxidation of the substrate after treatment of an insulating film by plasma H01L21/3105 and subgroups
• CPC Class Codes: H01L 21/0237 Materials
• CPC Class Codes: H01L 21/02554 Oxides
• CPC Class Codes: H01L 21/02565 Oxide semiconducting materials not being Group 12/16 materials, e.g. ternary compounds
• CPC Class Codes: H01L 21/02631 Physical deposition at reduced pressure, e.g. MBE, sputtering, evaporation
• CPC Class Codes: H01L 29/04 characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes characterised by physical imperfections H01L29/30
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H01L 29/78693 the semiconducting oxide being amorphous

Abstract

Provided is a highly reliable semiconductor device which includes a transistor including an oxide semiconductor. The semiconductor device includes an oxide semiconductor layer; a gate insulating layer provided over the oxide semiconductor layer; a gate electrode layer overlapping with the oxide semiconductor layer with the gate insulating layer provided therebetween; an insulating layer being in contact with part of an upper surface of the oxide semiconductor layer, covering a side surface of the gate insulating layer and a side surface and an upper surface of the gate electrode layer, and having a lower oxygen-transmitting property than the gate insulating layer; a sidewall insulating layer provided on the side surface of the gate electrode layer with the insulating layer provided therebetween; a source electrode layer and a drain electrode layer which are electrically connected to the oxide semiconductor layer.

Claims

1. A semiconductor device comprising:

an oxide semiconductor layer;

a gate electrode layer over the oxide semiconductor layer and overlapping with the oxide semiconductor layer;

a gate insulating layer interposed between the oxide semiconductor layer and the gate electrode layer; and

an insulating layer on and in contact with a part of an upper surface of the oxide semiconductor layer, a side surface of the gate insulating layer and a side surface and an upper surface of the gate electrode layer,

wherein the insulating layer has a lower oxygen-transmitting property than the gate insulating layer.

3. The semiconductor device according to claim 1, further comprising:

a sidewall insulating layer on the side surface of the gate electrode layer, the insulating layer being interposed between the gate electrode layer and the sidewall insulating layer.

7. The semiconductor device according to claim 1,

wherein the insulating layer is a metal oxide film.

9. The semiconductor device according to claim 1,

wherein the insulating layer is an aluminum oxide film.

11. The semiconductor device according to claim 1, further comprising:

a source electrode layer and a drain electrode layer each in contact with the oxide semiconductor layer and on a opposite side of the gate electrode layer, the insulating layer being interposed between the gate electrode layer and each of the source electrode layer and the drain electrode layer.

13. A memory device including the semiconductor device according to claim 1.

2. A semiconductor device comprising:

an oxide semiconductor layer which is non-single-crystal and includes a crystalline component;

a gate electrode layer over the oxide semiconductor layer and overlapping with the oxide semiconductor layer;

a gate insulating layer interposed between the oxide semiconductor layer and the gate electrode layer; and

an insulating layer on and in contact with a part of an upper surface of the oxide semiconductor layer, a side surface of the gate insulating layer and a side surface and an upper surface of the gate electrode layer,

wherein the insulating layer has a lower oxygen-transmitting property than the gate insulating layer.

4. The semiconductor device according to claim 2, further comprising:

a sidewall insulating layer on the side surface of the gate electrode layer, the insulating layer being interposed between the gate electrode layer and the sidewall insulating layer.

5. The semiconductor device according to claim 2, further comprising:

a source electrode layer and a drain electrode layer in contact with the oxide semiconductor layer,

wherein, in regions of the oxide semiconductor layer in contact with the source electrode layer and the drain electrode layer, a ratio of a content of the crystalline component to a content of an amorphous component is lower than in a region overlapping with the gate electrode layer.

6. The semiconductor device according to claim 2,

wherein in the crystalline component, a c-axis is aligned in a direction parallel to a normal vector of a surface on which the oxide semiconductor layer is formed or a normal vector of a surface of the oxide semiconductor layer.

8. The semiconductor device according to claim 2,

wherein the insulating layer is a metal oxide film.

10. The semiconductor device according to claim 2,

wherein the insulating layer is an aluminum oxide film.

12. The semiconductor device according to claim 2, further comprising:

a source electrode layer and a drain electrode layer each in contact with the oxide semiconductor layer and on an opposite side of the gate electrode layer, the insulating layer being interposed between the gate electrode layer and each of the source electrode layer and the drain electrode layer.

14. A memory device including the semiconductor device according to claim 2.

15. A method for manufacturing a semiconductor device, comprising:

forming an oxide semiconductor layer on an insulating surface;

forming a gate insulating film over the oxide semiconductor layer;

forming a gate electrode layer over the gate insulating film and overlapping with the oxide semiconductor layer;

forming a gate insulating layer between the oxide semiconductor layer and the gate electrode layer by etching the gate insulating film using the gate electrode layer as a mask;

forming an insulating film on and in contact with part of an upper surface of the oxide semiconductor layer, a side surface of the gate insulating layer and a side surface and an upper surface of the gate electrode layer,

wherein the insulating film has a lower oxygen-transmitting property than the gate insulating layer.

16. The method for manufacturing a semiconductor device according to claim 15, further comprising:

forming a sidewall insulating layer on the side surface of the gate electrode layer, the insulating film being interposed between the gate electrode layer and the sidewall insulating layer.

17. The method for manufacturing the semiconductor device according to claim 15,

wherein the insulating film is a metal oxide film.

18. The method for manufacturing the semiconductor device according to claim 15,

wherein the insulating film is an aluminum oxide film.

19. The method for manufacturing the semiconductor device according to claim 15, wherein forming the insulating film comprises the steps of:

forming a metal film; and

subjecting the metal film to an oxygen doping treatment.