NANO MOSFET WITH TRENCH BOTTOM OXIDE SHIELDED AND THIRD DIMENSIONAL P-BODY CONTACT
First Claim
1. A semiconductor power device, comprising:
- a lightly doped layer of a first conductivity type formed on top of a heavily doped layer of the first conductivity type,one or more devices formed in the lightly doped layer, each device including a doped body region of a second conductivity type that is opposite the first conductivity type,one or more electrically insulated gate electrodes formed in one or more corresponding trenches in the lightly doped layer, and a source region, wherein each of the one or more trenches has a depth that extends in a first dimension, a width that extends in a second dimension and a length that extends in a third dimension, wherein the first dimension is perpendicular to a plane of the heavily doped layer and wherein the second and third dimensions are parallel to the plane of the heavily doped layer;
wherein the doped body region is formed adjacent to one or more of the trenches proximate an upper surface of the lightly doped layer;
wherein the source region is formed proximate the upper surface and adjacent to one or more of the trenches extending along the third dimension; and
one or more deep heavily doped contacts of the second conductivity type formed at one or more locations proximate one or more of the trenches along the third dimension, wherein the one or more deep heavily doped contacts extend in the first direction from a surface below a top surface of the gate electrodes into a portion of the lightly doped layer substantially a same depth as a bottom of the doped body region, wherein the one or more deep heavily doped contacts are in electrical contact with the source region.
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Accused Products
Abstract
A semiconductor power device may include a lightly doped layer formed on a heavily doped layer. One or more devices are formed in the lightly doped layer. Each device may include a body region, a source region, and one or more gate electrodes formed in corresponding trenches in the lightly doped region. Each of the trenches has a depth in a first dimension, a width in a second dimension and a length in a third dimension. The body region is of opposite conductivity type to the lightly and heavily doped layers. The source region is formed proximate the upper surface. One or more deep contacts are formed at one or more locations along the third dimension proximate one or more of the trenches. The contacts extend in the first direction from the upper surface into the lightly doped layer and are in electrical contact with the source region.
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Citations
47 Claims
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1. A semiconductor power device, comprising:
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a lightly doped layer of a first conductivity type formed on top of a heavily doped layer of the first conductivity type, one or more devices formed in the lightly doped layer, each device including a doped body region of a second conductivity type that is opposite the first conductivity type, one or more electrically insulated gate electrodes formed in one or more corresponding trenches in the lightly doped layer, and a source region, wherein each of the one or more trenches has a depth that extends in a first dimension, a width that extends in a second dimension and a length that extends in a third dimension, wherein the first dimension is perpendicular to a plane of the heavily doped layer and wherein the second and third dimensions are parallel to the plane of the heavily doped layer; wherein the doped body region is formed adjacent to one or more of the trenches proximate an upper surface of the lightly doped layer; wherein the source region is formed proximate the upper surface and adjacent to one or more of the trenches extending along the third dimension; and one or more deep heavily doped contacts of the second conductivity type formed at one or more locations proximate one or more of the trenches along the third dimension, wherein the one or more deep heavily doped contacts extend in the first direction from a surface below a top surface of the gate electrodes into a portion of the lightly doped layer substantially a same depth as a bottom of the doped body region, wherein the one or more deep heavily doped contacts are in electrical contact with the source region. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19)
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20. A semiconductor power device, comprising:
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a lightly doped layer of a first conductivity type formed on top of a heavily doped layer of the first conductivity type, one or more devices formed in the lightly doped layer, each device including a doped body region, one or more electrically insulated gate electrodes formed in one or more corresponding trenches in the lightly doped layer, a source region, wherein each of the one or more trenches has a depth that extends in a first dimension, a width that extends in a second dimension and a length that extends in a third dimension, wherein the first dimension is perpendicular to a plane of the heavily doped layer and wherein the second and third dimensions are parallel to the plane of the heavily doped layer; wherein the doped body region is formed adjacent to one or more of the trenches proximate an upper surface of the lightly doped layer, wherein the body region is of a second conductivity type that is opposite the first conductivity type; wherein the one or more trenches comprises a first trench and a second trench adjacent to the first trench, wherein the source region comprises a first heavily doped of the first conductivity type formed proximate the upper surface extending from a side wall of the first trench to a side wall of the second trench adjacent the first trench and a second heavily doped region of the first conductivity type adjacent to the side wall of the first trench extending along the third dimension; one or more deep heavily doped contacts of the second conductivity type formed at one or more locations proximate one or more of the trenches along the third dimension, wherein the one or more deep heavily doped contacts extend in the first direction from a surface below a top surface of the gate electrode into a portion of the lightly doped layer. - View Dependent Claims (21, 22)
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23. A method for manufacturing a semiconductor power device, comprising:
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forming one or more trenches in a lightly doped layer of a first conductivity type on top of a heavily doped layer of the first conductivity type; forming one or more electrically insulated gate electrodes in the one or more trenches, wherein each of the one or more trenches has a depth that extends in a first dimension, a width that extends in a second dimension and a length that extends in a third dimension, wherein the first dimension is perpendicular to a plane of the heavily doped layer and wherein the second and third dimensions are parallel to the plane of the heavily doped layer; forming a doped body region adjacent to one or more of the trenches proximate an upper surface of the lightly doped layer, wherein the body region is of a second conductivity type that is opposite to the first conductivity type; forming a source region proximate the upper surface and adjacent to one or more of the one or more trenches, wherein the source region includes a first heavily doped source region of the first conductivity type formed proximate the upper surface extending from a side wall of a first of the one or more trenches to a side wall of a second of the one or more trenches adjacent the first trench and a second heavily doped source region of the first conductivity type adjacent to the side wall of the first trench extending along the third dimension; and forming one or more deep heavily doped contacts at one or more locations proximate one or more of the trenches along the third dimension, wherein the one or more deep heavily doped contacts extend in the first direction into the lightly doped layer, wherein the one or more deep heavily doped contacts are in electrical contact with the source region. - View Dependent Claims (24, 25, 26, 27, 28, 29, 30, 31)
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32. A method for manufacturing a semiconductor power device, comprising:
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forming one or more trenches in a lightly doped layer of a first conductivity type on top of a heavily doped layer of the first conductivity type; forming one or more electrically insulated gate electrodes in the one or more trenches, wherein each of the one or more trenches has a depth that extends in a first dimension, a width that extends in a second dimension and a length that extends in a third dimension, wherein the first dimension is perpendicular to a plane of the heavily doped layer and wherein the second and third dimensions are parallel to the plane of the heavily doped layer; forming a doped body region adjacent to one or more of the trenches proximate an upper surface of the lightly doped layer, wherein the body region is of a second conductivity type that is opposite to the first conductivity type; forming a source region proximate the upper surface and adjacent to one or more of the trenches, wherein the source region is heavily doped of the first conductivity type; forming one or more deep heavily doped contacts at one or more locations proximate one or more of the trenches along the third dimension, wherein the one or more deep heavily doped contacts extend in the first direction from the upper surface into the lightly doped layer, wherein the one or more deep heavily doped contacts are in electrical contact with the source region; forming an elongated opening in the source region in a mesa adjacent one or more of the one or more trenches, wherein a portion of the doped body region in the opening is exposed from the source region; and forming an active cell contact in the elongated opening in the mesa wherein the active cell contact is in electrical contact with one or more of the one or more deep heavily doped contacts. - View Dependent Claims (33, 34, 35, 36, 37, 38, 39)
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40. A method for manufacturing a semiconductor power device, comprising:
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forming one or more trenches in a lightly doped layer of a first conductivity type on top of a heavily doped layer of the first conductivity type; forming one or more electrically insulated gate electrodes in the one or more trenches with a top surface of the gate electrode etched back to a level below the upper surface of the lightly doped layer, wherein each of the one or more trenches has a depth that extends in a first dimension, a width that extends in a second dimension and a length that extends in a third dimension, wherein the first dimension is perpendicular to a plane of the heavily doped layer and wherein the second and third dimensions are parallel to the plane of the heavily doped layer; etching back the lightly doped layer to a level below the top surface of the gate electrode; forming a doped body region adjacent to one or more of the trenches proximate an upper surface of the etched lightly doped layer, wherein the body region is of a second conductivity type opposite to the first conductivity type; forming one or more deep heavily doped contacts at one or more locations proximate one or more of the trenches along the third dimension, wherein the one or more deep heavily doped contacts extend in the first direction from the upper surface into the lightly doped layer; and forming a Schottky contact in a mesa adjacent one or more of the one or more trenches, wherein the one or more deep heavily doped contacts are in electrical contact with the Schottky contact. - View Dependent Claims (41, 42, 43, 44, 45, 46, 47)
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Specification