SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

• US 20130200523A1
• Filed: 09/14/2012
• Published: 08/08/2013
• Est. Priority Date: 02/08/2012
• Status: Active Grant

• Current Assignee: Amkor Technology Taiwan Limited (Amkor Technology Incorporated)
• Original Assignee: Shigenori Sawachi
• Inventors: Yamagata, Osamu, Inoue, Hiroshi, Itakura, Satoru, Katsumata, Akio, SAWACHI, Shigenori, Chikai, Tomoshige, Hori, Masahiko
• Granted Patent: US 8,872,350 B2
• Time in Patent Office: Days
• US Class Current: 257/774
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 2224/06135 Covering only the peripheral area of the surface to be connected, i.e. peripheral arrangements
• CPC Class Codes: H01L 2224/12105 Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
• CPC Class Codes: H01L 2224/24226 the HDI interconnect connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the item being planar
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/32245 the item being metallic
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48145 the bodies being stacked
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2224/73267 Layer and HDI connectors
• CPC Class Codes: H01L 2224/82031 by chemical means, e.g. etching, anodisation
• CPC Class Codes: H01L 2224/82039 using a laser
• CPC Class Codes: H01L 2224/92244 the second connecting process involving a build-up interconnect
• CPC Class Codes: H01L 2225/06524 Electrical connections formed on device or on substrate, e.g. a deposited or grown layer
• CPC Class Codes: H01L 2225/06548 Conductive via connections through the substrate, container, or encapsulation
• CPC Class Codes: H01L 2225/06562 at least one device in the stack being rotated or offset
• CPC Class Codes: H01L 2225/06586 Housing with external bump or bump-like connectors
• CPC Class Codes: H01L 2225/06589 Thermal management, e.g. cooling
• CPC Class Codes: H01L 2225/1023 : the support being an insulating substrate
• CPC Class Codes: H01L 2225/1029 : the support being a lead frame
• CPC Class Codes: H01L 2225/1035 : the device being entirely enclosed by the support, e.g. high-density interconnect [HDI]
• CPC Class Codes: H01L 23/49816 : Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 23/5384 : Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors H01L23/5383, H01L23/5385 take precedence; pins attached to insulating substrates H01L23/49811
• CPC Class Codes: H01L 23/5389 : the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 24/24 : of an individual high density interconnect connector
• CPC Class Codes: H01L 24/82 : by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI] interconnection structure between a plurality of semiconductor chips H01L23/5389
• CPC Class Codes: H01L 24/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/00015 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed as prior art
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/12044 : OLED
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA

Abstract

A semiconductor device containing: a semiconductor element; a support substrate; an insulating material layer for sealing the semiconductor element and a periphery thereof; a metal thin film wiring layer provided in the insulating material layer, with a part thereof being exposed on an external surface; and metal vias provided in the insulating material layer and electrically connected to the metal thin film wiring layer. The semiconductor element is provided in a plurality of units and the respective semiconductor elements are stacked via an insulating material such that a circuit surface of each semiconductor element faces the metal thin film wiring layer, and electrode pads of each semiconductor element are exposed without being hidden by the semiconductor element stacked thereabove.

Claims

1. A semiconductor device, comprising:

a semiconductor element;

a support substrate;

an insulating material layer for sealing the semiconductor element and a periphery thereof;

a metal thin film wiring layer provided in the insulating material layer, with a part thereof being exposed on an external surface; and

metal vias provided in the insulating material layer and electrically connected to the metal thin film wiring layer, wherein

the semiconductor element is provided in a plurality, and the respective semiconductor elements are stacked via an insulating material such that a circuit surface of each semiconductor element faces the metal thin film wiring layer, and

electrode pads of each semiconductor element are exposed without being hidden by the semiconductor element stacked thereabove, and electrically connected to the metal thin film wiring layer.

3. The semiconductor device according to claim 1, wherein the insulating material layer is formed of a plurality of insulating material layers made of respectively different insulating materials.

5. The semiconductor device according to claim 1, wherein the insulating material layer is formed of a photosensitive insulating resin layer and a non-photosensitive insulating resin layer.

7. The semiconductor device according to claim 1, wherein the support substrate is made of a metal material, and the support substrate is connected to a GND.

9. The semiconductor device according to claim 1, wherein the support substrate is made of an organic material or made of an organic material and a metal conductor.

11. The semiconductor device according to claim 9, wherein other semiconductor package or electronic component is stacked via the support substrate, and the semiconductor device is electrically connected to the other semiconductor package or electronic component via through-holes provided to the support substrate.

13. A method of manufacturing the semiconductor device according to claim 1, comprising the steps of:

stacking and fixing, on a support substrate, a plurality of semiconductor elements such that circuit surfaces thereof face a same direction, and electrode pads of each semiconductor element are exposed without being hidden by the other semiconductor element;

forming a first insulating material layer for sealing the semiconductor elements and peripheries thereof;

forming, in the first insulating material layer, openings for forming metal vias and openings for electrically connecting the electrode pads;

forming a metal thin film seed layer on the first insulating material layer surface;

filling a conductive material in the openings and forming a metal thin film wiring layer at predetermined areas on the metal thin film seed layer;

removing the metal thin film seed layer on the first insulating material layer surface except the areas where the metal thin film wiring layer is formed; and

forming a second insulating material layer on the first insulating material layer provided thereon with the metal thin film wiring layer.

2. A semiconductor device, comprising a plurality of unit structure components stacked on a support substrate, each unit structure component comprising:

a semiconductor element;

an insulating material layer for sealing the semiconductor element and a periphery thereof;

a metal thin film wiring layer provided in the insulating material layer, with apart of this metal thin film wiring layer being exposed on an external surface; and

metal vias provided in the insulating material layer and electrically connected to the metal thin film wiring layer, wherein

the semiconductor element is provided in a plurality, and the respective semiconductor elements are stacked such that a circuit surface of each semiconductor element faces the metal thin film wiring layer, and

electrode pads of each semiconductor element are exposed without being hidden by the semiconductor element stacked thereabove and electrically connected to the metal thin film wiring layer,

wherein the respective unit structure components are electrically connected by the metal vias.

4. The semiconductor device according to claim 2, wherein the insulating material layer is formed of a plurality of insulating material layers made of respectively different insulating materials.

6. The semiconductor device according to claim 2, wherein the insulating material layer is formed of a photosensitive insulating resin layer and a non-photosensitive insulating resin layer.

8. The semiconductor device according to claim 2, wherein the support substrate is made of a metal material, and the support substrate is connected to a GND.

10. The semiconductor device according to claim 2, wherein the support substrate is made of an organic material or made of an organic material and a metal conductor.

12. The semiconductor device according to claim 10, wherein other semiconductor package or electronic component is stacked via the support substrate, and the semiconductor device is electrically connected to the other semiconductor package or electronic component via through-holes provided to the support substrate.

14. A method of manufacturing the semiconductor device according to claim 2, comprising the steps of:

stacking and fixing, on a support substrate, a plurality of semiconductor elements such that circuit surfaces thereof face a same direction, and electrode pads of each semiconductor element are exposed without being hidden by the other semiconductor element;

forming a first insulating material layer for sealing the semiconductor elements and peripheries thereof;

forming, in the first insulating material layer, openings for forming metal vias and openings for electrically connecting the electrode pads;

forming a metal thin film seed layer on the first insulating material layer surface;

filling a conductive material in the openings and forming a metal thin film wiring layer at predetermined areas on the metal thin film seed layer;

removing the metal thin film seed layer on the first insulating material layer surface except the areas where the metal thin film wiring layer is formed; and

forming a second insulating material layer on the first insulating material layer formed thereon with the metal thin film wiring layer, whereby a semiconductor element stacked body is manufactured as a unit structure component; and

mounting a plurality of the unit structure components on the second insulating material layer by repeating the foregoing series of steps,

wherein the respective unit structure components are electrically connected by the metal vias.