NON-VOLATILE MEMORY DEVICE HAVING VERTICAL STRUCTURE AND METHOD OF OPERATING THE SAME

• US 20130201758A1
• Filed: 03/15/2013
• Published: 08/08/2013
• Est. Priority Date: 02/02/2009
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Kim, Doogon, Shim, Sunil, Kim, Hansoo, Cho, Wonseok, Jang, Jaehoon, Jeong, Jaehun
• Granted Patent: US 8,824,209 B2
• Time in Patent Office: Days
• US Class Current: 365/185.2
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: H01L 29/66825 with a floating gate H01L29/6684 takes precedence
• CPC Class Codes: H01L 29/7881 Programmable transistors with only two possible levels of programmation H01L29/7888 takes precedence
• CPC Class Codes: H10B 41/20 characterised by three-dimensional arrangements, e.g. with cells on different height levels
• CPC Class Codes: H10B 41/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 41/35 with a cell select transistor, e.g. NAND

Abstract

Provided is a method of operating a non-volatile memory device. The method includes applying a turn-on voltage to each of first and second string select transistors of a first NAND string, applying first and second voltages to third and fourth string select transistors of a second NAND string, respectively, and applying a high voltage to word lines connected with memory cells of the first and second NAND strings.

Claims

1. A method of programming a non-volatile memory device including a plurality of memory cell strings arranged in rows and columns, columns of the plurality of memory cell strings being coupled with a plurality of bit lines respectively, the method comprising:

applying a turn-on voltage to gates of at least two first select transistors of a first memory cell string among the plurality of memory cell strings, the at least two first select transistors being stacked in series along a direction vertical to a substrate;

applying a pass voltage or a program voltage to respective gates of memory cells of the first cell string, the memory cells being stacked in series along the direction vertical to the substrate between the substrate and a side of the at least two first select transistors;

applying a first voltage to at least one gate of at least one dummy memory cell of the first cell string, the at least one dummy memory cell being stacked in series along the direction vertical to the substrate between a side of the at least two first select transistors and a side of the memory cells; and

applying a ground voltage to a bit line coupled to the first memory cell string if one of the memory cells of the first cell string are to be programmed,

wherein the first voltage is lower than the pass voltage and the program voltage and higher than a ground voltage.

2. The method of claim 1, further comprising:

applying a second voltage to the bit line coupled to the first memory cell string if the memory cells of the first cell string are to be program-prevented,

wherein the second voltage is lower than the first voltage and higher than the ground voltage.

3. The method of claim 1, further comprising:

applying a turn-off voltage to gates of at least two second select transistors of a second memory cell string among the plurality of memory cell string; and

applying the pass voltage or the program voltage to respective gates of memory cells of the second memory cell string.

4. The method of claim 1, further comprising:

applying a third voltage to at least one gate of at least one third select transistor of the first memory cell string coupled between the substrate and another side of the memory cells, the at least one third select transistor being stacked in series along the direction vertical to the substrate.

5. The method of claim 4, further comprising:

applying a fourth voltage to a gate of a dummy memory cell of the first cell string, the dummy memory cell being stacked in series along the direction vertical to the substrate between the another side of the memory cells and the at least one third select transistor.

6. The method of claim 4, further comprising:

applying a fourth voltage to respective gates of two or more dummy memory cells of the first cell string, the two or more dummy memory cells being stacked in series along the direction vertical to the substrate between the another side of the memory cells and the at least two second select transistors.

7. A method of programming a non-volatile memory device including first and second memory cell groups and first and second select transistor groups coupled between the first and second memory cell groups and a bit line, the method comprising:

applying a first voltage to respective gates of at least two first select transistors of the first select transistor group coupled between the first memory cell group and the bit line, the at least two first select transistors being stacked in series along a direction vertical to a substrate; and

applying a second voltage to respective gates of at least two second select transistors of the second select transistor group coupled between the second memory cell group and the bit line, the at least two second select transistors being stacked in series along the direction vertical to the substrate;

applying a pass voltage or a program voltage to respective gates of first memory cells of the first memory cell group, the first memory cells being stacked in series along the direction vertical to the substrate;

applying the pass voltage or the program voltage to respective gates of second memory cells of the second memory cell group, the second memory cells being stacked in series along the direction vertical to the substrate;

applying a third voltage to at least one gate of at least one first dummy memory cell stacked in series along the direction vertical to the substrate between the first memory cell group and the first select transistor group; and

applying a fourth voltage to at least one gate of at least one second dummy memory cell stacked in series along the direction vertical to the substrate between the second memory cell group and the second select transistor group,

wherein the first voltage is lower than the program voltage and higher than a ground voltage,

wherein the second voltage is lower than the first voltage.

8. The method of claim 7, further comprising:

applying a ground voltage to the bit line if one of the first memory cells are to be programmed.

9. The method of claim 7, further comprising:

applying a program inhibit voltage to the bit line if the first memory cells are to be program-prevented,

wherein the program inhibit voltage is lower than the third voltage or the fourth voltage and higher than the ground voltage.

10. The method of claim 7, wherein the third voltage and the fourth voltage are lower than the pass voltage and the program voltage and higher than the first voltage and the second voltage.

11. The method of claim 7, further comprising:

applying a fifth voltage to at least one gate of at least one third select transistor of a third select transistor group coupled between the first memory cell group and the substrate, the at least one third select transistor being stacked in series along the direction vertical to the substrate; and

applying a sixth voltage to at least one gate of at least one fourth select transistor of a fourth select transistor group coupled between the second memory cell group and the substrate, the at least one fourth select transistor being stacked in series along the direction vertical to the substrate,

wherein the fifth voltage and the sixth voltage are lower than the first voltage.

12. The method of claim 11, further comprising:

applying a seventh voltage to a gate of a third dummy memory cell stacked in series along the direction vertical to the substrate between the first memory cell group and the third select transistor group; and

applying a eighth voltage to a gate of a fourth dummy memory cell stacked in series along the direction vertical to the substrate between the second memory cell group and the fourth select transistor group,

wherein the seventh voltage and the eighth voltage are lower than the pass voltage and the program voltage and higher than the first voltage and the second voltage.

13. The method of claim 11, further comprising:

applying a seventh voltage to respective gates of two or more third dummy memory cells stacked in series along the direction vertical to the substrate between the first memory cell group and the third select transistor group; and

applying a eighth voltage to respective gates of two or more fourth dummy memory cells stacked in series along the direction vertical to the substrate between the second memory cell group and the fourth select transistor group,

wherein the seventh voltage and the eighth voltage are lower than the pass voltage and the program voltage and higher than the first voltage and the second voltage.

14. A solid state drive comprising:

a nonvolatile memory including a plurality of nonvolatile memory groups, each of the plurality of nonvolatile memory groups including a plurality of nonvolatile memory chips; and

a controller configured to communicate with the plurality of nonvolatile memory groups through a plurality of channels respectively, select a channel from among the plurality of channels, and output a program command, data and an address to the selected channel,

wherein each of the nonvolatile memory chips includes;

a memory cell array;

a page buffer configured to store received data and apply first bias voltages to the memory cell array according to the stored data and received program command; and

a row decoder configured to apply second bias voltages to the memory cell array according to received address and the received program command,

wherein the memory cell array includes;

a substrate;

a plurality of memory cell groups arranged in rows and columns on the substrate, each memory cell group including a plurality of memory cells stacked in series along a direction vertical to the substrate;

a plurality of first select transistor groups coupled between the substrate and the plurality of memory cell groups respectively, each first select transistor group including at least one first select transistor stacked in series along the direction vertical to the substrate; and

a plurality of second select transistor groups coupled between the plurality of memory cell groups and a plurality of bit lines respectively, each second select transistor group including at least two second select transistors stacked in series along the direction vertical to the substrate,

wherein the row decoder applies a turn-on voltage to respective gates of second select transistors of a selected row of the plurality of first select transistor groups and apply a turn-off voltage to respective gates of second select transistors of unselected rows of the plurality of first select transistors according to received address and the received program command.

15. The non-volatile memory device of claim 14, wherein the row decoder applies a ground voltage to at least one bit line of the plurality of bit lines and applies a first voltage higher than the ground voltage to remaining bit lines of the plurality of bit lines according to the received address and the received program command,

wherein the at least one bit line corresponds to at least one memory cell to be programmed, and the remaining bit lines correspond to memory cells to be program-prevented.

16. The non-volatile memory device of claim 14, further comprising dummy memory cell groups coupled between the plurality of memory cell groups and the plurality of first select transistor groups respectively, each dummy memory cell group including at least one dummy memory cell stacked in series along the direction vertical to the substrate,

wherein the row decoder applies a second voltage higher than the first voltage to respective gates of dummy memory cells of the first dummy memory cell groups according to the received address and the received program command.

17. The non-volatile memory device of claim 14, further comprising dummy memory cell groups coupled between the plurality of memory cell groups and the plurality of second select transistor groups respectively, each dummy memory cell group including at least one dummy memory cell stacked in series along the direction vertical to the substrate,

wherein the row decoder applies a second voltage higher than the first voltage to respective gates of dummy memory cells of the first dummy memory cell groups according to the received address and the received program command.

18. The non-volatile memory device of claim 14, wherein the row decoder applies a program voltage or a pass voltage to respective gates of memory cells of the plurality of memory cell groups according to the received address and the received program command.