SENSE AMPLIFIER FOR NONVOLATILE SEMICONDUCTOR MEMORY DEVICE

• US 20130201761A1
• Filed: 12/14/2012
• Published: 08/08/2013
• Est. Priority Date: 02/06/2012
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: KIM, Eui-Seung, Kim, Ji-Sung, O, SeEun
• Granted Patent: US 9,001,588 B2
• Time in Patent Office: Days
• US Class Current: 365/185.17
• CPC Class Codes: G11C 11/56 using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
• CPC Class Codes: G11C 16/28 using differential sensing or reference cells, e.g. dummy cells

Abstract

A sense amplifier circuit of a nonvolatile semiconductor memory device is provided. The sense amplifier circuit includes a reference voltage generator, a sensing voltage generator and a comparator. The sensing voltage generator outputs a sensing voltage to a sensing node depending on a current flowing through a data line. A load transistor supplying a current to the data line is directly connected to a clamping node. The load transistor is included in a current mirror circuit. In a read operation, a low voltage drive operation is performed and a sensing speed and power consumption are properly controlled.

Claims

1. A sense amplifier circuit of a nonvolatile semiconductor memory device comprising:

a reference voltage generator configured to output a reference voltage to a reference node depending on a current flowing through a reference data line connected to a reference bit line;

a sensing voltage generator configured to output a sensing voltage to a sensing node depending on a current flowing through a data line connected to a bit line; and

a comparator configured to sense and amplify a difference between the reference voltage of the reference node and the sensing voltage of the sensing node to detect data stored in a memory cell connected to the bit line.

2. The sense amplifier circuit of claim 1, wherein the sensing voltage generator comprises:

a current supply part including a load transistor connected between a power supply part and a clamping node, wherein the current supply part is configured to be controlled by the sensing voltage of the sensing node; and

a regulating control part connected to the current supply part and the power supply part, wherein the regulating control part is configured to regulate a clamping voltage set to the clamping node.

3. The sense amplifier circuit of claim 2, wherein the load transistor of the current supply part is a PMOS transistor.

4. The sense amplifier circuit of claim 2, wherein the regulating control part comprises:

a first PMOS transistor which includes a gate and a drain connected to a gate of the load transistor and a source connected to the power supply part, wherein the first PMOS forms a current mirror structure together with the load transistor;

a first NMOS transistor which includes a drain connected to the drain of the first PMOS transistor;

a second NMOS transistor which includes a drain-source channel connected between a source of the first NMOS transistor and a ground terminal and a gate configured to receive a bias voltage; and

an inverter configured to output an inverting output depending on a voltage of the clamping node to a gate of the first NMOS transistor.

5. The sense amplifier circuit of claim 1, wherein the memory cell is included in a NOR flash memory cell array.

6. The sense amplifier circuit of claim 5, wherein the NOR flash memory cell array is built in a smart card.

7. The sense amplifier circuit of claim 1, wherein connection or disconnection between the bit line and the data line is performed by a column gate.

8. The sense amplifier circuit of claim 1, wherein when a voltage of the clamping node is set to be about 0.5V, a voltage of the power supply part is about 0.9V or less.

9. The sense amplifier circuit of claim 4, wherein the inverter comprises:

a PMOS transistor which includes a source connected to a first power supply voltage source and a gate configured to receive a bias voltage set; and

a NMOS transistor which includes a gate connected to the clamping node and a drain-source channel connected between an output connection node to which a drain of the PMOS transistor is connected and a ground terminal.

10. The sense amplifier circuit of claim 1, wherein the comparator includes a current mirror type differential amplifier which includes a first input terminal connected to the sensing node and a second input terminal connected to the reference node, wherein the comparator is configured to be driven in response to an enable signal.

16. The sense amplifier circuit of claim 2, wherein the load transistor is directly connected to the clamping node.

11. A nonvolatile semiconductor memory device comprising:

a memory cell array comprising memory cells arranged at intersections between a plurality of word lines and a plurality of bit lines;

a decoder configured to select a word line and a bit line of the memory cell array; and

a sense amplifier circuit configured to sense data stored in a selected memory cell by detecting a current flowing through a selected bit line,

wherein the sense amplifier circuit comprises;

a reference voltage generator configured to output a reference voltage to a reference node depending on a current flowing through a reference data line connected to a reference bit line;

a sensing voltage generator configured to output a sensing voltage to a sensing node depending on a current flowing through a data line connected to a bit line; and

a comparator configured to sense and amplify a difference between the reference voltage of the reference node and the sensing voltage of the sensing node to detect data stored in a memory cell connected to the bit line.

12. The nonvolatile semiconductor memory device of claim 11, wherein the sensing voltage generator comprises:

a current supply part including a load transistor connected between a power supply part and a clamping node, wherein the current supply part is configured to be controlled by the sensing voltage of the sensing node; and

a regulating control part connected to the current supply part and the power supply part, wherein the regulating control part is configured to regulate a clamping voltage set to the clamping node.

13. The nonvolatile semiconductor memory device of claim 12, wherein the regulating control part comprises:

a first PMOS transistor which includes a gate and a drain connected to a gate of the load transistor and a source connected to the power supply part, wherein the first PMOS forms a current mirror structure together with the load transistor;

a first NMOS transistor which includes a drain connected to the drain of the first PMOS transistor;

a second NMOS transistor which includes a drain-source channel connected between a source of the first NMOS transistor and a ground terminal and a gate configured to receive a bias voltage; and

an inverter configured to output an inverting output depending on a voltage of the clamping node to a gate of the first NMOS transistor.

14. The nonvolatile semiconductor memory device of claim 11, wherein the memory cell array includes a NOR flash memory cell array embedded in a system.

15. The nonvolatile semiconductor memory device of claim 11, wherein a current flowing through the reference data line of the reference voltage generator is determined by a reference cell connected to the reference bit line.

17. A sense amplifier circuit of a semiconductor memory device comprising:

a reference voltage generator connected to a reference data line, wherein the reference voltage generator includes a current mirror having a load transistor connected to the reference data line;

a sensing voltage generator connected to a data line, wherein the sensing voltage generator includes a current mirror having a load transistor connected to the data line; and

a comparator configured to output sensing data in response to a reference voltage provided from the reference voltage generator and a sensing voltage provided from the sensing voltage generator.

18. The sense amplifier of claim 17, wherein the load transistor of the current mirror in the reference voltage generator is configured to be controlled by the reference voltage.

19. The sense amplifier of claim 17, wherein the load transistor of the current mirror in the sensing voltage generator is configured to be controlled by the sensing voltage.

20. The sense amplifier of claim 17, wherein the comparator is a differential amplifier.