Volatile Memory with a Decreased Consumption

• US 20130201771A1
• Filed: 02/04/2013
• Published: 08/08/2013
• Est. Priority Date: 02/03/2012
• Status: Active Grant

• Current Assignee: STMicroelectronics SA (STMicroelectronics NV)
• Original Assignee: STMicroelectronics SA (STMicroelectronics NV)
• Inventors: Feki, Anis, Lafont, Jean-Christophe, Turgis, David
• Granted Patent: US 8,891,317 B2
• Time in Patent Office: Days
• US Class Current: 365/189.011
• CPC Class Codes: G11C 11/419 Read-write [R-W] circuits
• CPC Class Codes: G11C 13/0069 Writing or programming circuits or methods
• CPC Class Codes: G11C 14/0054 in which the volatile element is a SRAM cell
• CPC Class Codes: G11C 7/00 Arrangements for writing information into, or reading information out from, a digital store G11C5/00 takes precedence; auxiliary circuits for stores using semiconductor devices G11C11/4063, G11C11/413
• CPC Class Codes: G11C 8/00 Arrangements for selecting an address in a digital store for stores using transistors G11C11/407, G11C11/413
• CPC Class Codes: G11C 8/12 Group selection circuits, e.g. for memory block selection, chip selection, array selection
• CPC Class Codes: G11C 8/14 Word line organisation; Word line lay-out
• CPC Class Codes: G11C 8/16 Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups

Abstract

A volatile memory including volatile memory cells adapted to the performing of data write and read operations. The memory cells are arranged in rows and in columns and, further, are distributed in separate groups of memory cells for each row. The memory includes a first memory cell selection circuit configured to perform write operations and a second memory cell selection circuit, different from the first circuit, configured to perform read operations. The first circuit is capable of selecting, for each row, memory cells from one of the group of memory cells for a write operation. The second circuit is capable of selecting, for each row, memory cells from one of the groups of memory cells for a read operation.

Claims

1. A volatile memory (25;

45) comprising volatile memory cells (20;

30;

40) adapted to performing data write and read operations, the memory cells being arranged in rows and columns and, further, being distributed in separate groups of memory cells for each row, the memory comprising a first memory cell selection circuit (PG0L, PG0R, PG1L, PG1R;

PU, PD, PG2L, PG2R;

WL_MUX, PGL, PGR) configured to perform write operations and a second memory cell selection circuit (RPDL, RPDR), different from the first circuit, configured to perform read operations, wherein the first circuit is capable of selecting, for each row, memory cells from one of the group of memory cells for a write operation, the second circuit being capable of selecting, for each row, memory cells from one of the groups of memory cells for a read operation.

2. The volatile memory of claim 1, wherein the second selection circuit comprises read word lines (RWL_MUX) for each row, each read word line being connected to all the memory cells (20;

30;

40) of one of the groups of memory cells.

3. The volatile memory of claim 2, wherein each memory cell (20;

30;

40) comprises;

first and second inverters, the output of the first inverter (INVL) being connected to the input (IL) of the second inverter and the output of the second inverter (INVR) being connected to the input (IR) of the first inverter;

a first switch (PG1L;

PG2L;

PGL) connected to the output of the first inverter;

a second switch (PG1R;

PG2R;

PGR) connected to the output of the second inverter;

a first MOS transistor (RPDL) having second first conduction terminals and a first gate, the first gate being connected to the output of the first inverter;

a second MOS transistor (RPDR) having two second conduction terminals and a second gate, the second gate being connected to the output of the second inverter,

and wherein each read word line (RWL_MUX) is connected to one of the first conduction terminals and to one of the second conduction terminals, and wherein the first selection circuit (PG0L, PG0R, PG1L, PG1R;

PU, PD, PG2L, PG2R;

WL_MUX, PGL, PGR) comprises a circuit capable of turning on the first and second switches of one of the groups of memory cells.

4. The volatile memory of claim 3, comprising first and second read bit lines (RBLT, RBLF) for each column and wherein, for at least some memory cells of each column, the other one of the first conduction terminals of the first MOS transistor (RPDL) is connected to the first read bit line and the other one of the second conduction terminals of the second MOS transistor (RPDR) is connected to the second read bit line.

5. The volatile memory of claim 3, wherein the first switch comprises a third MOS transistor (PG1L;

PG2L;

PGL) connecting the output (IL) of the first inverter (INVL) to a first write bit line (BLT) and wherein the second switch comprises a fourth MOS transistor (PG1R;

PG2R;

PGR) connecting the output (IR) of the second inverter (INVR) to a second write bit line (BLF).

6. The volatile memory of claim 5, wherein the first selection circuit comprises write word lines (WL_MUX) for each row, each write word line being connected to the gates of the third and fourth MOS transistors (PGL, PGR) of the memory cells of one of the groups of memory cells.

7. The volatile memory of claim 5, wherein the first selection circuit comprises a third inverter (PU, PD), the output of the third inverter being connected to the gates of the third and fourth transistors (PG2L, PG2R) and the input of the third inverter being connected to a write word line (WL).

8. The volatile memory of claim 5, wherein the first selection transistor comprises a fifth MOS transistor (PG0L) interposed between the third MOS transistor (PG1L) and the first write bit line (BLT) and a sixth MOS transistor (PG0R) interposed between the fourth MOS transistor (PG1R) and the second write bit line (BLF).

9. An electronic device comprising a battery and the memory (25;

45) of claim 1, powered by the battery.

10. A method for reading data stored in the memory (25;

45) of claim 2, comprising, for a memory row, the setting to a first level (GND) of one of the read word lines (RWL_MUX) associated with the row while the other read word lines associated with the row are maintained at a second level (VDD) greater than the first level.