PROGRAMMABLE LOGIC DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE

• US 20130207170A1
• Filed: 01/31/2013
• Published: 08/15/2013
• Est. Priority Date: 02/09/2012
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Kurokawa, Yoshiyuki
• Granted Patent: US 9,379,113 B2
• Time in Patent Office: Days
• US Class Current: 257/296
• CPC Class Codes: H01L 21/82 to produce devices, e.g. integrated circuits, each consisting of a plurality of components
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 27/105 including field-effect components
• CPC Class Codes: H01L 27/11807 CMOS gate arrays
• CPC Class Codes: H01L 27/11898 Input and output buffer/driver structures
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 28/40 Capacitors
• CPC Class Codes: H03K 19/0008 Arrangements for reducing power consumption
• CPC Class Codes: H03K 19/1735 by wiring, e.g. uncommitted logic arrays
• CPC Class Codes: H03K 19/1737 using multiplexers H03K19/1738 takes precedence
• CPC Class Codes: H03K 19/17728 Reconfigurable logic blocks, e.g. lookup tables
• CPC Class Codes: H03K 19/17748 Structural details of configuration resources
• CPC Class Codes: H03K 19/1776 for memories
• CPC Class Codes: H10B 10/125 the MOSFET being a thin film transistor [TFT]
• CPC Class Codes: H10B 10/18 Peripheral circuit regions

Abstract

To provide a programmable logic device in which the number of elements per bit in a memory array can be reduced and with which power consumption or operation frequency can be estimated accurately at a testing stage. Provided is a programmable logic device including a plurality of programmable logic elements and a memory array which stores configuration data that determines logic operation executed in the plurality of programmable logic elements. The memory array includes a plurality of memory elements. The memory element includes a node which establishes electrical connection between the programmable logic element and the memory array, a switch for supplying charge whose amount is determined by the configuration data to the node, holding the charge in the node, or releasing the charge from the node, and a plurality of wirings. Capacitance is formed between the node and the wiring.

Claims

1. A semiconductor device comprising:

a programmable logic element; and

a memory element comprising;

an electrode electrically connected to the programmable logic element;

an insulating film over the electrode;

a first wiring over the electrode and the insulating film; and

a second wiring over the electrode and the insulating film.

2. The semiconductor device according to claim 1,

wherein the memory element comprises a contact in the insulating film,

wherein the electrode is electrically connected to one of the first wiring and the second wiring through the contact depending on configuration data,

wherein the memory element is configured to supply a voltage corresponding to the configuration data from the electrode to the programmable logic element, and

wherein the programmable logic element is configured to execute an operation determined by the voltage corresponding to the configuration data.

3. The semiconductor device according to claim 2,

wherein the first wiring is configured to supply a first voltage, and

wherein the second wiring is configured to supply a second voltage.

4. The semiconductor device according to claim 1,

wherein the memory element comprises a switch comprising a terminal electrically connected to the electrode.

5. The semiconductor device according to claim 4,

wherein the memory element is configured to store configuration data,

wherein the memory element is configured to supply a voltage corresponding to the configuration data from the electrode to the programmable logic element, and

wherein the programmable logic element is configured to execute an operation determined by the voltage corresponding to the configuration data.

6. The semiconductor device according to claim 5,

wherein a first capacitance is formed between the electrode and the first wiring and is configured to hold first charge corresponding to the configuration data, and

wherein a second capacitance is formed between the electrode and the second wiring and is configured to hold second charge corresponding to the configuration data.

7. The semiconductor device according to claim 6,

wherein the first wiring is configured to supply a first voltage, and

wherein the second wiring is configured to supply a second voltage.

8. The semiconductor device according to claim 4,

wherein the switch comprises a transistor whose off-state current is smaller than about 40 fA when a drain voltage is 3.3 V.

9. The semiconductor device according to claim 4,

wherein the switch comprises a transistor comprising an oxide semiconductor in a channel formation region.

10. A method for manufacturing a semiconductor device, comprising the steps of:

forming a programmable logic element;

forming an electrode;

forming an insulating film over the electrode;

forming a contact in the insulating film; and

forming a first wiring and a second wiring over the electrode and the insulating film,

wherein the electrode is electrically connected to one of the first wiring and the second wiring through the contact depending on first configuration data,

wherein the electrode is configured to supply a voltage corresponding to the first configuration data to the programmable logic element, and

wherein the programmable logic element is configured to execute an operation determined by the voltage corresponding to the first configuration data.

11. The method for manufacturing a semiconductor device according to claim 10,

wherein the first wiring is configured to supply a first voltage, and

wherein the second wiring is configured to supply a second voltage.

12. The method for manufacturing a semiconductor device according to claim 10,

wherein the first configuration data is determined by using a second semiconductor device comprising:

a second programmable logic element; and

a second memory element comprising;

a second electrode electrically connected to the second programmable logic element;

a transistor comprising a first terminal and a second terminal, the second terminal of the transistor being electrically connected to the second electrode;

a second insulating film over the second electrode;

a third wiring over the second electrode and the second insulating film; and

a fourth wiring over the second electrode and the second insulating film,

wherein the first configuration data is determined by the steps of;

supplying a first gate signal to a gate of the transistor to turn on the transistor;

supplying a data signal corresponding to second configuration data to the first terminal of the transistor;

storing a first charge corresponding to the second configuration data to a first capacitance formed between the second electrode and the third wiring;

storing a second charge corresponding to the second configuration data to a second capacitance formed between the second electrode and the fourth wiring,

supplying a second gate signal to the gate of the transistor to turn off the transistor;

supplying a voltage corresponding to the second configuration data to the second programmable logic element from the second electrode;

performing an operation of the second programmable logic element determined by the second configuration data; and

determining the second configuration data as the first configuration data when the second programmable logic element performs a desired operation.

13. The method for manufacturing a semiconductor device according to claim 12,

wherein the first wiring is configured to supply a first voltage, and

wherein the second wiring is configured to supply a second voltage.

14. The method for manufacturing a semiconductor device according to claim 12,

wherein off-state current of the transistor is smaller than about 40 fA when a drain voltage is 3.3 V.

15. The method for manufacturing a semiconductor device according to claim 12,

wherein the transistor comprises an oxide semiconductor in a channel formation region.

16. A method for manufacturing a semiconductor device, comprising the steps of:

forming a programmable logic element;

forming an electrode;

forming a transistor comprising a first terminal and a second terminal;

forming an insulating film over the electrode; and

forming a first wiring and a second wiring over the electrode and the insulating film,

wherein a first capacitance is formed between the electrode and the first wiring and is configured to hold first charge corresponding to first configuration data,

wherein a second capacitance is formed between the electrode and the second wiring and is configured to hold second charge corresponding to the first configuration data,

wherein the electrode is electrically connected to the second terminal of the transistor and is configured to supply a voltage corresponding to the first configuration data to the programmable logic element, and

wherein the programmable logic element is configured to execute an operation determined by the voltage corresponding to the first configuration data.

17. The method for manufacturing a semiconductor device according to claim 16,

wherein the first wiring is configured to supply a first voltage, and

wherein the second wiring is configured to supply a second voltage.

18. The method for manufacturing a semiconductor device according to claim 16,

wherein the first configuration data is determined by the steps of:

supplying a first gate signal to a gate of the transistor to turn on the transistor;

supplying a data signal corresponding to second configuration data to the first terminal of the transistor;

storing a third charge corresponding to the second configuration data to the first capacitance;

storing a fourth charge corresponding to the second configuration data to the second capacitance,

supplying a second gate signal to the gate of the transistor to turn off the transistor;

supplying a voltage corresponding to the second configuration data to the programmable logic element from the electrode;

performing an operation of the programmable logic element determined by the second configuration data; and

determining the second configuration data as the first configuration data when the programmable logic element performs a desired operation.

19. The method for manufacturing a semiconductor device according to claim 18,

wherein a second semiconductor device is manufactured by the steps of:

forming a second programmable logic element;

forming a second electrode;

forming a second insulating film over the second electrode;

forming a second contact; and

forming a third wiring and a fourth wiring over the second electrode and the second insulating film,

wherein the second electrode is electrically connected to one of the third wiring and the fourth wiring through the second contact depending on the first configuration data,

wherein the second electrode is configured to supply a voltage corresponding to the first configuration data to the second programmable logic element, and

wherein the second programmable logic element is configured to execute an operation determined by the voltage corresponding to the first configuration data.

20. The method for manufacturing a semiconductor device according to claim 19,

wherein the transistor comprises an oxide semiconductor in a channel formation region.