Semiconductor Device and Method of Forming a Shielding Layer Over a Semiconductor Die After Forming a Build-up Interconnect Structure

• US 20130207247A1
• Filed: 03/18/2013
• Published: 08/15/2013
• Est. Priority Date: 12/10/2008
• Status: Active Grant

• Current Assignee: JCET Semiconductor (Shaoxing) Co., Ltd.
• Original Assignee: Stats Chippac Limited
• Inventors: Pagaila, Reza A., Huang, Rui, Lin, Yaojian
• Granted Patent: US 8,790,962 B2
• Time in Patent Office: Days
• US Class Current: 257/659
• CPC Class Codes: H01L 21/56 Encapsulations, e.g. encapsulation layers, coatings
• CPC Class Codes: H01L 21/565 Moulds
• CPC Class Codes: H01L 2224/0554 External layer
• CPC Class Codes: H01L 2224/0555 Shape
• CPC Class Codes: H01L 2224/0556 Disposition
• CPC Class Codes: H01L 2224/0557 the external layer being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05571 the external layer being disposed in a recess of the surface
• CPC Class Codes: H01L 2224/05573 Single external layer
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/05611 Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/05624 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05639 Silver [Ag] as principal constituent
• CPC Class Codes: H01L 2224/05644 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/05647 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05655 Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16237 the bump connector connecting to a bonding area disposed in a recess of the surface of the item
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 : connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73207 : Bump and wire connectors
• CPC Class Codes: H01L 2224/73265 : Layer and wire connectors
• CPC Class Codes: H01L 2224/81005 : being a temporary or sacrificial substrate
• CPC Class Codes: H01L 23/3121 : a substrate forming part of the encapsulation
• CPC Class Codes: H01L 23/3128 : the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/552 : Protection against radiation, e.g. light or electromagnetic waves
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 25/0655 : the devices being arranged next to each other
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01004 : Beryllium [Be]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01023 : Vanadium [V]
• CPC Class Codes: H01L 2924/01024 : Chromium [Cr]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/0103 : Zinc [Zn]
• CPC Class Codes: H01L 2924/01046 : Palladium [Pd]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01073 : Tantalum [Ta]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/01322 : Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/09701 : Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: H01L 2924/12041 : LED
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/1306 : Field-effect transistor [FET]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15174 : in different layers of the multilayer substrate
• CPC Class Codes: H01L 2924/15192 : Resurf arrangement of the internal vias
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/207 : Diameter ranges
• CPC Class Codes: H01L 2924/3011 : Impedance
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding

Abstract

A semiconductor device is made by forming an interconnect structure over a substrate. A semiconductor die is mounted to the interconnect structure. The semiconductor die is electrically connected to the interconnect structure. A ground pad is formed over the interconnect structure. An encapsulant is formed over the semiconductor die and interconnect structure. A shielding cage can be formed over the semiconductor die prior to forming the encapsulant. A shielding layer is formed over the encapsulant after forming the interconnect structure to isolate the semiconductor die with respect to inter-device interference. The shielding layer conforms to a geometry of the encapsulant and electrically connects to the ground pad. The shielding layer can be electrically connected to ground through a conductive pillar. A backside interconnect structure is formed over the interconnect structure, opposite the semiconductor die.

Claims

1. A method of making a semiconductor device, comprising:

providing a first interconnect structure including a ground pad;

disposing a semiconductor die over the first interconnect structure; and

forming a shielding layer over the semiconductor die and first interconnect structure to isolate the semiconductor die with respect to inter-device interference, the shielding layer being electrically coupled to the ground pad.

2. The method of claim 1, further including depositing an encapsulant over the semiconductor die and first interconnect structure.

3. The method of claim 1, further including disposing a shielding cage over the semiconductor die to isolate the semiconductor die with respect to inter-device interference.

4. The method of claim 1, further including forming a second interconnect structure between the semiconductor die and shielding layer.

5. The method of claim 1, further including forming a second interconnect structure between the first interconnect structure and shielding layer.

6. The method of claim 1, wherein the ground pad includes an island or ring formed around a peripheral region of the first interconnect structure.

7. A method of making a semiconductor device, comprising:

providing a first interconnect structure;

disposing a semiconductor die over the first interconnect structure; and

disposing a shielding layer over the semiconductor die and first interconnect structure to isolate the semiconductor die with respect to inter-device interference.

8. The method of claim 7, further including forming a ground pad over the first interconnect structure, wherein the shielding layer is electrically coupled to the ground pad.

9. The method of claim 7, further including depositing an encapsulant over the semiconductor die and first interconnect structure.

10. The method of claim 7, further including disposing a shielding cage over the semiconductor die to isolate the semiconductor die with respect to inter-device interference.

11. The method of claim 7, further including forming a second interconnect structure between the semiconductor die and shielding layer.

12. The method of claim 7, further including forming a second interconnect structure between the first interconnect structure and shielding layer.

13. The method of claim 7, wherein the ground pad includes an island or ring formed around a peripheral region of the first interconnect structure.

14. A semiconductor device, comprising:

a first interconnect structure including a ground pad;

a semiconductor die disposed over the first interconnect structure; and

a shielding layer disposed over the semiconductor die and first interconnect structure to isolate the semiconductor die with respect to inter-device interference, the shielding layer being electrically coupled to the ground pad.

15. The semiconductor device of claim 14, further including an encapsulant deposited over the semiconductor die and first interconnect structure.

16. The semiconductor device of claim 14, further including a shielding cage disposed over the semiconductor die to isolate the semiconductor die with respect to inter-device interference.

17. The semiconductor device of claim 14, further including a second interconnect structure formed between the semiconductor die and shielding layer.

18. The semiconductor device of claim 14, further including a second interconnect structure formed between the first interconnect structure and shielding layer.

19. The semiconductor device of claim 14, wherein the ground pad includes an island or ring formed around a peripheral region of the first interconnect structure.

20. A semiconductor device, comprising:

a first interconnect structure;

a semiconductor die disposed over the first interconnect structure; and

a shielding layer disposed over the semiconductor die and first interconnect structure to isolate the semiconductor die with respect to inter-device interference.

21. The semiconductor device of claim 20, further including a ground pad formed over the first interconnect structure, wherein the shielding layer is electrically coupled to the ground pad.

22. The semiconductor device of claim 20, further including an encapsulant deposited over the semiconductor die and first interconnect structure.

23. The semiconductor device of claim 20, further including a shielding cage disposed over the semiconductor die to isolate the semiconductor die with respect to inter-device interference.

24. The semiconductor device of claim 20, further including a second interconnect structure formed between the first interconnect structure and shielding layer.

25. The semiconductor device of claim 20, wherein the ground pad includes an island or ring formed around a peripheral region of the first interconnect structure.