Method and Apparatus for Adjusting Drain Bias of A Memory Cell With Addressed and Neighbor Bits

• US 20130208552A1
• Filed: 02/13/2012
• Published: 08/15/2013
• Est. Priority Date: 02/13/2012
• Status: Active Grant

• Current Assignee: Macronix International Co., Ltd.
• Original Assignee: Macronix International Co., Ltd.
• Inventors: Chen, Han-Sung, Chen, Chung-Kuang, Hung, Chun-Hsiung
• Granted Patent: US 8,913,445 B2
• Time in Patent Office: Days
• US Class Current: 365/189.15
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 11/5671 using charge trapping in an insulator
• CPC Class Codes: G11C 2211/5621 Multilevel programming verification
• CPC Class Codes: G11C 7/00 Arrangements for writing information into, or reading information out from, a digital store G11C5/00 takes precedence; auxiliary circuits for stores using semiconductor devices G11C11/4063, G11C11/413

Abstract

The storage layer such as a nitride layer of a nonvolatile memory cell has two storage parts storing separately addressable data, typically respectively proximate to the source terminal and the drain terminal. The applied drain voltage while sensing the data of one of the storage parts depends on the data stored at the other storage part. If the data stored at the other storage part is represented by a threshold voltage exceeding a minimum threshold voltage, then the applied drain voltage is raised. This technology is useful in read operations and program verify operations to widen the threshold voltage window.

Claims

1. An integrated circuit, comprising:

a nonvolatile memory cell including;

a first current carrying terminal, a second current carrying terminal, and a gate;

a first storage part proximate to the first current carrying terminal and storing first data; and

a second storage part proximate to the second current carrying terminal and storing second data;

control circuitry applying a read bias arrangement to the first current carrying terminal, the second current carrying terminal, and the gate, the read bias arrangement applied to read one of the first data and the second data, the read bias arrangement depending on the other of the first data and the second data.

2. The integrated circuit of claim 1,

wherein the first data determines a first voltage applied to the first current carrying terminal in the read bias arrangement applied to read the second data, and

wherein the second data determines a second voltage applied to the second current carrying terminal in the read bias arrangement applied to read the first data.

3. The integrated circuit of claim 1, wherein responsive to the first data being represented by a first threshold voltage of the first storage part exceeding a minimum threshold voltage, a first voltage is applied to the first current carrying terminal in the read bias arrangement applied to read the second data,

responsive to the first data being represented by a second threshold voltage of the first storage part not exceeding a minimum threshold voltage, a second voltage is applied to the first current carrying terminal in the read bias arrangement applied to read the second data, and

the first voltage is higher than the second voltage.

4. The integrated circuit of claim 3, further comprising:

a memory storing data bits determined by whether the first data is represented by a threshold voltage that exceeds a minimum threshold voltage, wherein the control circuitry reads the data bits from the memory to control whether the first voltage or the second voltage is applied to the first current carrying terminal in the read bias arrangement applied to read the second data.

5. The integrated circuit of claim 1, wherein the first data and the second data each are one of a plurality of data values, the plurality of data values having a first total of data values, the plurality of data values represented by a plurality of programmed threshold voltage ranges, the plurality of programmed threshold voltage ranges having a second total of programmed threshold voltage ranges, the second total exceeding the first total.

6. The integrated circuit of claim 1, wherein the first data and the second data each are one of a plurality of data values, the plurality of data values represented by a plurality of programmed threshold voltage ranges, a data value of the plurality of data values represented by multiple programmed threshold voltage ranges from the plurality of programmed threshold voltage ranges.

7. The integrated circuit of claim 1, wherein the first data and the second data each are one of a plurality of data values, the plurality of data values represented by a plurality of programmed threshold voltage ranges, a data value of the plurality of data values represented by multiple programmed threshold voltage ranges from the plurality of programmed threshold voltage ranges, the first data represented by a particular one of the multiple programmed threshold voltage ranges depending on the second data.

8. The integrated circuit of claim 1, wherein the first storage part and the second storage part are different parts of a nitride storage layer.

9. The integrated circuit of claim 1, wherein each of the first data and the second data are multiple bits.

10. The integrated circuit of claim 1, wherein prior to applying the read bias arrangement depending on the other of the first data and the second data, a read operation determines the other of the first data and the second data.

11. An integrated circuit, comprising:

a nonvolatile memory cell including;

a first current carrying terminal, a second current carrying terminal, and a gate;

a first storage part proximate to the first current carrying terminal and storing first data; and

a second storage part proximate to the second current carrying terminal and storing second data;

control circuitry applying a program verify bias arrangement to the first current carrying terminal, the second current carrying terminal, and the gate, the program verify bias arrangement applied to program verify one of the first data and the second data, the program verify bias arrangement depending on the other of the first data and the second data.

12. The integrated circuit of claim 11, wherein the first data determines a first voltage applied to the first current carrying terminal in the program verify bias arrangement applied to program verify the second data, and

wherein the second data determines a second voltage applied to the second current carrying terminal in the program verify bias arrangement applied to program verify the first data.

13. The integrated circuit of claim 11, wherein responsive to the first data being represented by a first threshold voltage of the first storage part exceeding a minimum threshold voltage, a first voltage is applied to the first current carrying terminal in the program verify bias arrangement applied to program verify the second data,

wherein responsive to the first data being represented by a second threshold voltage of the first storage part not exceeding a minimum threshold voltage, a second voltage is applied to the first current carrying terminal in the program verify bias arrangement applied to program verify the second data, and

the first voltage is higher than the second voltage.

14. The integrated circuit of claim 13, further comprising:

a memory storing data bits determined by whether the first data is represented by a threshold voltage that exceeds a minimum threshold voltage, wherein the control circuitry reads the data bits from the memory to control whether the first voltage or the second voltage is applied to the first current carrying terminal in the program verify bias arrangement applied to program verify the second data.

15. The integrated circuit of claim 11, wherein the first data and the second data each are one of a plurality of data values, the plurality of data values having a first total of data values, the plurality of data values represented by a plurality of programmed threshold voltage ranges, the plurality of programmed threshold voltage ranges having a second total of programmed threshold voltage ranges, the second total exceeding the first total.

16. The integrated circuit of claim 11, wherein the first data and the second data each are one of a plurality of data values, the plurality of data values represented by a plurality of programmed threshold voltage ranges, a data value of the plurality of data values represented by multiple programmed threshold voltage ranges from the plurality of programmed threshold voltage ranges.

17. The integrated circuit of claim 11, wherein the first data and the second data each are one of a plurality of data values, the plurality of data values represented by a plurality of programmed threshold voltage ranges, a data value of the plurality of data values represented by multiple programmed threshold voltage ranges from the plurality of programmed threshold voltage ranges, the first data represented by a particular one of the multiple programmed threshold voltage ranges depending on the second data.

18. The integrated circuit of claim 11, wherein the first storage part and the second storage part are different parts of a nitride storage layer.

19. The integrated circuit of claim 11, wherein each of the first data and the second data are multiple bits.

20. The integrated circuit of claim 11, wherein prior to applying the program verify bias arrangement depending on the other of the first data and the second data, input data of a programming command determines the other of the first data and the second data.

21. The integrated circuit of claim 11, wherein prior to applying the program verify bias arrangement depending on the other of the first data and the second data, a read operation determines the other of the first data and the second data.

22. A memory method, comprising:

applying a read bias arrangement to a first current carrying terminal, a second current carrying terminal, and a gate of a nonvolatile memory cell, the read bias arrangement applied to read one of first data and the second data, the read bias arrangement depending on the other of the first data and the second data, the first data stored at a first storage part proximate to the first current carrying terminal and the second data stored at a second storage part proximate to the second current carrying terminal.

23. A memory method, comprising:

applying a program verify bias arrangement to a first current carrying terminal, a second current carrying terminal, and a gate of a nonvolatile memory cell, the program verify bias arrangement applied to program verify one of first data and the second data, the program verify bias arrangement depending on the other of the first data and the second data, the first data stored at a first storage part proximate to the first current carrying terminal and the second data stored at a second storage part proximate to the second current carrying terminal.