METHOD FOR ROBUST PREAMBLE LOCATION IN A DQS SIGNAL
First Claim
1. A method for capturing a Data Lane Signal (DQ) by determining a preamble location in a Data Strobe Signal (DQS), comprising:
- using a computer device or processor to perform the steps of;
receiving a maximum delay value and a step size;
sampling said DQS at said maximum delay value;
sampling said DQS in a sequence of delay values, a greatest delay value in said sequence of delay values being one step size less than said maximum delay value, each delay value of said sequence of delay values being one step size less than a proximal delay value, said sequence of delay values beginning with said greatest delay value;
storing at least one delay value when said sampling indicates said DQS was at a high;
storing at least one delay value when said sampling indicates said DQS was at a low;
storing at least one delay value when said sampling indicates said DQS made a transition from said high to said low;
determining and storing an earliest location of said transition from said high to said low;
storing a preamble location and discontinuing said sampling when, during a single clock cycle, said sampling indicates a number of consecutive instances of said DQS being at said low, said number of consecutive instances based on a multiple of said step size; and
capturing a DQ based on said stored preamble location and said earliest location of said transition from said high to said low.
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Abstract
A method for robust preamble location and gate training in a Double Data Rate type Three (DDR3) computing environment. A single algorithm is employed to begin sampling a Data Strobe Signal (DQS) at a maximum delay value designed to fall within the driven region of a DQS. The method then begins sampling the DQS in a sequence of delay values from right to left. Each result of the sampling indicating a high state and a low state are stored as well as the occasions where the DQS transitioned from high to low indicating a rising edge. At a consecutive number of samples returning a low state, the method determines the preamble has been reached and discontinues sampling. The method retains the most recently stored rising edge as the first rising edge and configures the result for gate training.
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Citations
20 Claims
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1. A method for capturing a Data Lane Signal (DQ) by determining a preamble location in a Data Strobe Signal (DQS), comprising:
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using a computer device or processor to perform the steps of; receiving a maximum delay value and a step size; sampling said DQS at said maximum delay value; sampling said DQS in a sequence of delay values, a greatest delay value in said sequence of delay values being one step size less than said maximum delay value, each delay value of said sequence of delay values being one step size less than a proximal delay value, said sequence of delay values beginning with said greatest delay value; storing at least one delay value when said sampling indicates said DQS was at a high; storing at least one delay value when said sampling indicates said DQS was at a low; storing at least one delay value when said sampling indicates said DQS made a transition from said high to said low; determining and storing an earliest location of said transition from said high to said low; storing a preamble location and discontinuing said sampling when, during a single clock cycle, said sampling indicates a number of consecutive instances of said DQS being at said low, said number of consecutive instances based on a multiple of said step size; and capturing a DQ based on said stored preamble location and said earliest location of said transition from said high to said low. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A method for gate training in a Double Data Rate type Three (DDR3) environment and for simultaneously determining a location of a preamble in a plurality of Data Strobe Signals (DQS) across a corresponding plurality of data lanes, the method comprising:
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using a computer device or processor to perform the steps of; receiving a maximum delay value and a step size; sampling said plurality of DQS at said maximum delay value; sampling, concurrently and in parallel, said plurality of DQS in a sequence of delay values, a greatest delay value in said sequence of delay values being one step size less than said maximum delay value, each delay value of said sequence of delay values being one step size less than a proximal delay value, said sequence of delay values beginning with said greatest delay value; storing at least one delay value when said sampling indicates said DQS was at a high; storing at least one delay value when said sampling indicates said DQS was at a low; storing at least one delay value when said sampling indicates said DQS made a transition from said high to said low; determining and storing an earliest location of said transition from said high to said low; training a series of gates corresponding to said plurality of data lanes based on a result of said determining and storing an earliest location of said transition; storing a preamble location and discontinuing said sampling for each of said plurality of DQS when, during a single clock cycle, said sampling indicates a number of consecutive instances of said DQS being at said low, said number of consecutive instances based on a multiple of said step size; and capturing, concurrently and in parallel, a plurality of Data Signals (DQ) based on said stored preamble location and said earliest location of said transition from said high to said low. - View Dependent Claims (12, 13, 14, 15, 16, 17, 18, 19, 20)
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Specification