ENHANCED DEBUGGING FOR EMBEDDED DEVICES
First Claim
1. A machine implemented method at a debug host device, the method comprising:
- accessing, via a hardware integrated debug framework, data in volatile random access memory of a debug target device;
accessing, via the hardware integrated debug framework, data in nonvolatile random access electrically erasable semiconductor memory of the debug target device;
accessing, via the hardware integrated debug framework, one or more registers of one or more processors on the debug target device; and
creating, on the debug host device, a debug target system snapshot comprising the volatile memory data, nonvolatile memory data, and data from one or more registers of one or more processors on the debug target device, wherein the debug target device has malfunctioned due to a failure.
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Accused Products
Abstract
Methods, machine-readable tangible storage media, and data processing systems that enable a debug host device to acquire memory dump information from a debug target device after the target device suffers an unrecoverable system malfunction are disclosed. In one embodiment, data in the volatile memory on a debug target device is accessed via a hardware integrated debug framework, which is also used to access data on a nonvolatile electronically erasable semiconductor memory of a debug target device, and one or more registers of one or more processors on a debug target device, and a core dump is created on the debug host device.
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Citations
26 Claims
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1. A machine implemented method at a debug host device, the method comprising:
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accessing, via a hardware integrated debug framework, data in volatile random access memory of a debug target device; accessing, via the hardware integrated debug framework, data in nonvolatile random access electrically erasable semiconductor memory of the debug target device; accessing, via the hardware integrated debug framework, one or more registers of one or more processors on the debug target device; and creating, on the debug host device, a debug target system snapshot comprising the volatile memory data, nonvolatile memory data, and data from one or more registers of one or more processors on the debug target device, wherein the debug target device has malfunctioned due to a failure. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A machine implemented method at a debug host device, the method comprising:
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accessing, through an external debug interface on a debug target device, a hardware integrated debug framework of a system on a chip integrated circuit; copying, via the hardware integrated debug framework, a page table on one or more processors from the debug target device, to the debug host device, through the external debug interface; analyzing the page table entries to determine the subset of page mapped virtual addresses that contain kernel memory allocations; accessing, via the debug framework, one or more physical memory addresses containing kernel memory allocations on the debug target device; and copying, through the debug interface, one or more blocks of memory stored at the one or more physical memory addresses on the debug target device. - View Dependent Claims (9, 10)
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11. A non-transitory machine-readable storage medium having instructions stored therein, which when executed by a machine cause the machine to perform operations, the operations comprising:
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accessing data in the volatile random access system memory of a debug target device via a hardware integrated debug framework; accessing data on a nonvolatile random access electrically erasable semiconductor memory device of the debug target device via the hardware integrated debug framework; accessing one or more registers of one or more processors on the debug target device; and creating a debug target system snapshot on a debug host device, the debug target system snapshot comprising at least the system memory data, the nonvolatile memory data, and the data from one or more registers of one or more processors on the debug target device, wherein the debug target device has malfunctioned due to a failure. - View Dependent Claims (12, 13, 14, 15, 16)
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17. A non-transitory machine-readable storage medium having instructions stored therein, which when executed by a machine cause the machine to perform operations, the operations comprising:
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accessing, through an external debug interface, a hardware integrated debug framework; copying, via the hardware integrated debug framework, a page table on one or more processors from the debug target device to the debug host device, through the external debug interface; analyzing the page table entries to determine the subset of page mapped virtual addresses that contain kernel memory allocations by applying an algorithm to the set of page mapped virtual addresses, the algorithm comprising analyzing the set of page mapped virtual addresses to find a pattern of mappings, the pattern of mappings to indicate the presence of one or more kernel memory allocations. accessing, via the debug framework, one or more physical memory addresses containing kernel memory allocations on the debug target device; and copying, through the debug interface, one or more blocks of memory stored at the one or more physical memory addresses on the debug target device. - View Dependent Claims (18)
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19. A debugging system for embedded devices, the system comprising:
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a debug host device comprising one or more processors, a main system memory, and a nonvolatile storage device; a hardware debug device coupled with the debug host device, the hardware debug device to provide a debug interface between a debug host device and one or more debug target devices; a debug target device comprising a system on a chip integrated circuit, volatile DRAM memory, and nonvolatile electrically erasable semiconductor memory, wherein the system on a chip integrated circuit comprises one or more processors and a hardware integrated debug framework, the hardware integrated debug framework to allow the hardware debug device and debug host device to control the one or more processors of the system on a chip integrated circuit after the debug target device malfunctions due to an operating system level failure; and a debug console, attached to the debug host device, to monitor debug output from the debug target device. - View Dependent Claims (20, 21, 22, 23, 24, 25, 26)
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Specification