SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

• US 20130214270A1
• Filed: 02/11/2013
• Published: 08/22/2013
• Est. Priority Date: 11/07/2008
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: YAMAZAKI, Shunpei, AKIMOTO, Kengo, KAWAE, Daisuke
• Granted Patent: US 8,803,146 B2
• Time in Patent Office: Days
• US Class Current: 257/43
• CPC Class Codes: H01L 21/02554 Oxides
• CPC Class Codes: H01L 21/02565 Oxide semiconducting materials not being Group 12/16 materials, e.g. ternary compounds
• CPC Class Codes: H01L 21/02631 Physical deposition at reduced pressure, e.g. MBE, sputtering, evaporation
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/1288 employing particular masking sequences or specially adapted masks, e.g. half-tone mask
• CPC Class Codes: H01L 29/41733 for thin film transistors with insulated gate
• CPC Class Codes: H01L 29/4908 for thin film semiconductor, e.g. gate of TFT
• CPC Class Codes: H01L 29/786 Thin film transistors, i.e. transistors with a channel being at least partly a thin film transistors having only the source or the drain region on an insulator layer H01L29/0653; thin film FinFETs H01L29/785
• CPC Class Codes: H01L 29/78618 characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure silicide contacts, electrodes in general H01L29/458
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621
• CPC Class Codes: H10K 10/46 Field-effect transistors, e.g. organic thin-film transistors [OTFT] H10K10/43 takes precedence
• CPC Class Codes: H10K 10/462 Insulated gate field-effect transistors [IGFETs]
• CPC Class Codes: H10K 10/466 Lateral bottom-gate IGFETs comprising only a single gate
• CPC Class Codes: H10K 10/84 Ohmic electrodes, e.g. source or drain electrodes

Abstract

A structure by which electric-field concentration which might occur between a source electrode and a drain electrode in a bottom-gate thin film transistor is relaxed and deterioration of the switching characteristics is suppressed, and a manufacturing method thereof. A bottom-gate thin film transistor in which an oxide semiconductor layer is provided over a source and drain electrodes is manufactured, and angle θ1 of the side surface of the source electrode which is in contact with the oxide semiconductor layer and angle θ2 of the side surface of the drain electrode which is in contact with the oxide semiconductor layer are each set to be greater than or equal to 20° and less than 90°, so that the distance from the top edge to the bottom edge in the side surface of each electrode is increased.

Claims

1. (canceled)

2. A semiconductor device comprising:

a glass substrate;

a transistor over the glass substrate, the transistor comprising;

a gate electrode;

a first insulating layer over the gate electrode;

an oxide semiconductor layer over the first insulating layer; and

a source electrode and a drain electrode each electrically connected to the oxide semiconductor layer;

a second insulating layer over the transistor;

a pixel electrode over the second insulating layer;

a third insulating layer over the pixel electrode;

a light-emitting layer over the pixel electrode and the third insulating layer;

an electrode over the light-emitting layer,

wherein the oxide semiconductor layer comprises indium and zinc,

wherein each of a side surface of the source electrode and a side surface of the drain electrode has a tapered shape,

wherein a first angle of the tapered shape that is made between the side surface of the source electrode and an upper surface of the glass substrate is greater than or equal to 20° and

smaller than or equal to 90°

, and

wherein a second angle of the tapered shape that is made between the side surface of the drain electrode and the upper surface of the glass substrate is greater than or equal to 20° and

smaller than or equal to 90°

.

3. The semiconductor device according to claim 2, wherein each of the source electrode and the drain electrode is in contact with an upper surface of the first insulating layer.

4. The semiconductor device according to claim 2, wherein the oxide semiconductor layer is over the source electrode and the drain electrode.

5. The semiconductor device according to claim 2, wherein the oxide semiconductor layer is in contact with each of the side surface of the source electrode and the side surface of the drain electrode.

6. The semiconductor device according to claim 2, wherein the oxide semiconductor layer further comprises gallium.

7. The semiconductor device according to claim 2, wherein the pixel electrode is in contact with the drain electrode.

8. The semiconductor device according to claim 2, wherein the oxide semiconductor layer is a non-single-crystal film.

9. The semiconductor device according to claim 2, further comprising:

a first buffer layer between the oxide semiconductor layer and the source electrode; and

a second buffer layer between the oxide semiconductor layer and the drain electrode,

wherein each of the first buffer layer and the second buffer layer has lower resistivity than the oxide semiconductor layer.

10. A semiconductor device comprising:

a glass substrate;

a transistor over the glass substrate, the transistor comprising;

a gate electrode;

a first insulating layer over the gate electrode;

an oxide semiconductor layer over the first insulating layer; and

a source electrode and a drain electrode each electrically connected to the oxide semiconductor layer;

a second insulating layer over the transistor;

a pixel electrode over the second insulating layer;

a third insulating layer over the pixel electrode;

a light-emitting layer over the pixel electrode and the third insulating layer;

an electrode over the light-emitting layer,

wherein the oxide semiconductor layer comprises indium and zinc,

wherein each of a side surface of the source electrode and a side surface of the drain electrode has a step in a lower portion thereof,

wherein a first angle of the step that is made between the side surface of the source electrode and an upper surface of the glass substrate is greater than or equal to 20° and

smaller than or equal to 90°

, and

wherein a second angle of the step that is made between the side surface of the drain electrode and the upper surface of the glass substrate is greater than or equal to 20° and

smaller than or equal to 90°

.

11. The semiconductor device according to claim 10, wherein each of the source electrode and the drain electrode is in contact with an upper surface of the first insulating layer.

12. The semiconductor device according to claim 10, wherein the oxide semiconductor layer is over the source electrode and the drain electrode.

13. The semiconductor device according to claim 10, wherein the oxide semiconductor layer is in contact with each of the side surface of the source electrode and the side surface of the drain electrode.

14. The semiconductor device according to claim 10, wherein the oxide semiconductor layer further comprises gallium.

15. The semiconductor device according to claim 10, wherein the pixel electrode is in contact with the drain electrode.

16. The semiconductor device according to claim 10, wherein the oxide semiconductor layer is a non-single-crystal film.

17. The semiconductor device according to claim 10, further comprising:

a first buffer layer between the oxide semiconductor layer and the source electrode; and

a second buffer layer between the oxide semiconductor layer and the drain electrode,

wherein each of the first buffer layer and the second buffer layer has lower resistivity than the oxide semiconductor layer.

18. A semiconductor device comprising:

a glass substrate;

a transistor over the glass substrate, the transistor comprising;

a gate electrode;

a first insulating layer over the gate electrode;

an oxide semiconductor layer over the first insulating layer; and

a source electrode and a drain electrode each electrically connected to the oxide semiconductor layer;

a second insulating layer over the transistor;

a pixel electrode over the second insulating layer;

a third insulating layer over the pixel electrode;

a light-emitting layer over the pixel electrode and the third insulating layer;

an electrode over the light-emitting layer,

wherein the oxide semiconductor layer comprises indium and zinc,

wherein a first angle between a surface of the glass substrate and a side surface of a first bottom edge of the source electrode is made to be different from an angle between the surface of the glass substrate and a side surface of a top edge of the source electrode, and

wherein a second angle between the surface of the glass substrate and a side surface of a second bottom edge of the drain electrode is made to be different from an angle between the surface of the glass substrate and a side surface of a top edge of the drain electrode.

19. The semiconductor device according to claim 18, wherein each of the source electrode and the drain electrode is in contact with an upper surface of the first insulating layer.

20. The semiconductor device according to claim 18, wherein the oxide semiconductor layer is over the source electrode and the drain electrode.

21. The semiconductor device according to claim 18, wherein the oxide semiconductor layer is in contact with each of the side surface of the source electrode and the side surface of the drain electrode.

22. The semiconductor device according to claim 18, wherein the oxide semiconductor layer further comprises gallium.

23. The semiconductor device according to claim 18, wherein the pixel electrode is in contact with the drain electrode.

24. The semiconductor device according to claim 18, wherein the oxide semiconductor layer is a non-single-crystal film.

25. The semiconductor device according to claim 18, further comprising:

a first buffer layer between the oxide semiconductor layer and the source electrode; and

a second buffer layer between the oxide semiconductor layer and the drain electrode,

wherein each of the first buffer layer and the second buffer layer has lower resistivity than the oxide semiconductor layer.