Dual Gate Lateral MOSFET

• US 20130214352A1
• Filed: 02/20/2012
• Published: 08/22/2013
• Est. Priority Date: 02/20/2012
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Chen, Po-Yu
• Granted Patent: US 9,159,786 B2
• Time in Patent Office: Days
• US Class Current: 257/335
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/66704 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7825 with trench gate electrode trench gate electrodes per se H01L29/4236

Abstract

A dual gate lateral MOSFET comprises a drift region over a substrate, an isolation region formed in the drift region and a channel region formed in the drift region. The dual gate lateral MOSFET comprises a drain region formed in the drift region and a source region formed in the channel region, wherein the source region and drain region are formed on opposing sides of the isolation region. The dual gate lateral MOSFET further comprises a first gate and a second gate formed adjacent to the source region, wherein the first gate and the second gate are stacked together and separated by a dielectric layer.

Claims

1. A semiconductor device comprising:

a substrate of a first conductivity;

a first region of a second conductivity formed over the substrate;

a body region of the first conductivity formed in the first region;

an isolation region formed in the first region;

a second region of the second conductivity formed in the first region;

a third region of the second conductivity formed in the first region, wherein the third region and the second region are formed on opposing sides of the isolation region;

a first dielectric layer formed over the first region;

a first gate formed over the first dielectric layer;

a second dielectric layer formed over the first gate; and

a second gate formed over the second dielectric layer.

2. The semiconductor device of claim 1, wherein the first gate and the second gate are separated by the second dielectric layer.

3. The semiconductor device of claim 1, wherein:

the first conductivity is P type; and

the second conductivity is N type.

4. The semiconductor device of claim 1, further comprising a sidewall spacer formed between the second gate and the third region.

5. The semiconductor device of claim 1, where:

the second region is a drain; and

the third region is a source.

6. The semiconductor device of claim 1, wherein the second gate and the third region is separated by a thin dielectric layer.

7. The semiconductor device of claim 1, wherein the body region is of a doping density in a range from about 10¹⁶/cm³ to about 5×

10¹⁷/cm³.

8. The semiconductor device of claim 1, wherein:

the second region and the third region are of a doping density in a range from about 10¹⁹/cm³ to about 5×

10¹⁹/cm³.

9. The semiconductor device of claim 1, wherein the first region is an epitaxial layer grown from the substrate.

10. A device comprising:

a drift region having a first conductivity type formed over a substrate;

an isolation region formed in the drift region;

a drain region having the first conductivity type formed in the drift region;

a channel region having a second conductivity type formed in the drift region;

a source region having the first conductivity type formed in the channel region, wherein the source region and drain region are formed on opposing sides of the isolation region; and

a first gate and a second gate formed adjacent to the source region, wherein the first gate and the second gate are stacked together and separated by a dielectric layer.

11. The device of claim 10, wherein:

the first conductivity type is an n-type conductivity; and

the second conductivity type is a p-type conductivity.

12. The device of claim 10, wherein:

the first conductivity type is a p-type conductivity; and

the second conductivity type is an n-type conductivity.

13. The device of claim 10, further comprising:

a sidewall spacer formed between the second gate the source region.

14. The device of claim 10, wherein the channel region is of a doping density in a range from about 10¹⁶/cm³ to about 5×

10¹⁷/cm³.

15. The device of claim 10, wherein:

the drain region and the source region are of a doping density in a range from about 10¹⁹/cm³ to about 5×

10′

⁹/cm³.

16. A method comprising:

providing a substrate with a first conductivity type;

growing an epitaxial layer with a second conductivity type on the substrate;

forming an isolation region in the epitaxial layer;

forming a body region with the first conductivity type in the epitaxial layer;

implanting ions with the second conductivity type to form a drain region in the epitaxial layer;

implanting ions with the second conductivity type to form a source region in the body region, wherein the source region and the drain region are on opposing sides of the isolation region; and

forming a dual gate structure adjacent to the source region.

17. The method of claim 16, further comprising:

forming a sidewall spacer along an edge of the dual gate structure, wherein the sidewall spacer isolates the dual gate structure from the source region.

18. The method of claim 16, further comprising:

forming a trench in the epitaxial layer using a first etching process;

forming a bottom dielectric layer in the trench;

filling a dielectric material in the trench;

removing a portion of the dielectric material in the trench;

forming a middle dielectric layer; and

filing the dielectric material on the middle dielectric layer.

19. The method of claim 16, further comprising:

forming the body region between the isolation region and the dual gate structure.

20. The method of claim 16, wherein the dual gate structure comprises a second gate stacked on a first gate.