AREA AND POWER SAVING STANDARD CELL METHODOLOGY

• US 20130214380A1
• Filed: 04/09/2013
• Published: 08/22/2013
• Est. Priority Date: 09/13/2007
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Malek-Khosravi, Behnam, Brunolli, Michael
• Granted Patent: US 8,893,063 B2
• Time in Patent Office: Days
• US Class Current: 257/499
• CPC Class Codes: G06F 30/327 Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist
• CPC Class Codes: H01L 27/04 the substrate being a semiconductor body

Abstract

A semiconductor integrated circuit including a circuit for adaptive power supply regulation and designed using a process that increases operating speed used for characterizing circuit operation at a slow corner. In some embodiments a slow corner voltage is set to a higher than expected level for timing analysis performed by automated design tools.

Claims

1. A method for designing integrated circuits, comprising:

receiving a register transfer level (RTL) description of a circuit;

synthesizing the RTL description by selecting cells from a standard cell library to implement functions in accordance with the RTL description, the selection of cells based in part on timing requirements indicated by the RTL description;

determining if the selected cells meet the timing requirements indicated by the RTL description for both a slow corner and a fast corner, the slow corner being determined at least in part by a slow process parameter, a slow voltage parameter, and a slow temperature parameter, the fast corner being determined at least in part by a fast process parameter, a fast voltage parameter, and a fast temperature parameter, with the slow voltage parameter approximate the fast voltage parameter.

2. A semiconductor integrated circuit, the semiconductor integrated circuit including a circuit for adaptive voltage regulation, the semiconductor integrated circuit including gates in standard cells selected by a process that uses a higher than normal voltage in performing timing analysis for a slow corner.

3. The semiconductor integrated circuit of claim 2, wherein the process uses a lower than normal voltage in performing timing analysis for a fast corner.

4. The semiconductor integrated circuit of claim 2 wherein the circuit for adaptive voltage regulation comprises an adaptive power supply regulation circuit.