METHOD OF FORMING SUBSTRATE CONTACT FOR SEMICONDUCTOR ON INSULATOR (SOI) SUBSTRATE

• US 20130214382A1
• Filed: 03/18/2013
• Published: 08/22/2013
• Est. Priority Date: 12/03/2010
• Status: Active Grant

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: International Business Machines Corporation
• Inventors: Wang, Geng, Booth, Roger A. Jr., Cheng, Kangguo, Ervin, Joseph, Pei, Chengwen, Todi, Ravi M.
• Granted Patent: US 9,293,520 B2
• Time in Patent Office: Days
• US Class Current: 257/506
• CPC Class Codes: H01L 21/02529 Silicon carbide
• CPC Class Codes: H01L 21/02532 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/0262 Reduction or decomposition of gaseous compounds, e.g. CVD
• CPC Class Codes: H01L 21/743 Making of internal connections, substrate contacts
• CPC Class Codes: H01L 21/76224 using trench refilling with dielectric materials trench filling with polycristalline silicon H01L21/763; together with vertical isolation, e.g. trench refilling in a SOI substrate H01L21/76264
• CPC Class Codes: H01L 21/76229 Concurrent filling of a plurality of trenches having a different trench shape or dimension, e.g. rectangular and V-shaped trenches, wide and narrow trenches, shallow and deep trenches
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 28/40 Capacitors
• CPC Class Codes: H01L 28/91 made by depositing layers, e.g. by depositing alternating conductive and insulating layers
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/66181 Conductor-insulator-semiconductor capacitors, e.g. trench capacitors
• CPC Class Codes: H10B 12/0387 Making the trench

Abstract

A semiconductor structure is provided that includes a material stack including an epitaxially grown semiconductor layer on a base semiconductor layer, a dielectric layer on the epitaxially grown semiconductor layer, and an upper semiconductor layer present on the dielectric layer. A capacitor is present extending from the upper semiconductor layer through the dielectric layer into contact with the epitaxially grown semiconductor layer. The capacitor includes a node dielectric present on the sidewalls of the trench and an upper electrode filling at least a portion of the trench. A substrate contact is present in a contact trench extending from the upper semiconductor layer through the dielectric layer and the epitaxially semiconductor layer to a doped region of the base semiconductor layer. A substrate contact is also provided that contacts the base semiconductor layer through the sidewall of a trench. Methods for forming the above-described structures are also provided.

Claims

1. A semiconductor structure comprising:

a material stack comprising an n-type semiconductor layer on a base semiconductor layer, a dielectric layer on the n-type semiconductor layer, and an upper semiconductor layer present on the dielectric layer;

a capacitor present in a capacitor trench extending from the upper semiconductor layer through the dielectric layer into contact with the n-type semiconductor layer, wherein the capacitor comprises a node dielectric present on the sidewalls of the trench and an upper electrode filling at least a portion of the trench; and

a substrate contact present in a contact trench extending from the upper semiconductor layer through the dielectric layer and the n-type semiconductor layer to a p-type doped region of the base semiconductor layer.

2. The semiconductor structure of claim 1, wherein the base semiconductor layer comprises a semiconducting material selected from the group consisting of Si, strained Si, SiC, SiGe, SiGeC, Si alloys, Ge, Ge alloys, GaAs, InAs, InP, or a combination thereof.

3. The semiconductor structure of claim 1, wherein the n-type semiconductor layer is a semiconductor material that is selected from the group consisting of Si, strained Si, SiC, SiGe, SiGeC, Si alloys, Ge, Ge alloys, GaAs, InAs, InP, and a combination thereof.

4. The semiconductor structure of claim 1, wherein the n-type semiconductor layer is doped with phosphorus present in a concentration ranging from 1×

10¹⁸ atoms/cm³ to 5×

10²¹ atoms/cm³.

5. The semiconductor structure claim 1, wherein the n-type semiconductor layer has a thickness ranging from 1 μ

m to 5 μ

m.

6. The semiconductor structure of claim 1, wherein the dielectric layer is an oxide, nitride or oxynitride material.

7. The semiconductor structure of claim 1, wherein the dielectric layer has a thickness that ranges from 5.0 nm to 400.0 nm.

8. The semiconductor structure of claim 1, wherein the upper semiconductor layer comprises a semiconductor material selected from the group consisting of Si, strained Si, SiC, SiGe, SiGeC, Si alloys, Ge, Ge alloys, GaAs, InAs, InP, and a combination thereof.

9. The semiconductor structure of claim 1, wherein the upper semiconducting material has a thickness ranging from 5.0 nm to 200.0 nm.

10. The semiconductor structure of claim 1, wherein the n-type semiconductor layer has a thickness that is greater than 1.0 micron, the contact trench is at least twice as wide as the capacitor trench.

11. The semiconductor structure of claim 1, wherein a width of the capacitor trench ranges from 0.03 μ

m to 0.2 μ

m, and a width of the contact opening ranges from 0.10 μ

m to 0.5 μ

m.

12. The semiconductor structure of claim 1, wherein the p-type dopant that is present in the p-type dopant region is at a concentration ranging from 1×

10¹⁷ atoms/cm³ to 5×

10²¹ atoms/cm³.

13. The semiconductor structure of claim 1, wherein a metal nitride layer 65 is present in the contact trench and the capacitor trench that is selected from the group consisting of titanium nitride (TiN), tantalum nitride (TaN), tantalum silicon nitride (TaSiN), tungsten nitride (WN) and a combination thereof.

14. The semiconductor structure of claim 1, wherein the contact trench further comprises a silicide including Ni, Ti or a combination thereof.

15. A semiconductor structure comprising:

a semiconductor on insulator (SOI) substrate comprising an upper semiconductor layer, a buried dielectric layer, and a base semiconductor layer;

a substrate contact present in a first trench extending from an upper surface of the semiconductor layer through the buried dielectric layer into contact with the base semiconductor layer, wherein the substrate contact includes a conductive fill material that is in direct contact with the base semiconductor layer with a sidewall portion of the trench and is separated from the base portion of the trench by a conformal dielectric layer; and

a capacitor present in a second trench comprising a buried plate, a node dielectric and an upper electrode, wherein the node dielectric is present on an entirety of the sidewalls and base portions of the second trench that is present in the base semiconductor layer and is identical in composition to the conformal dielectric layer.

16. The semiconductor structure of claim 15, wherein the first trench has a first width and the second trench has a second width, wherein the first width is at least twice as wide as the second width.

17. The semiconductor structure of claim 15, wherein the first width is at least 0.2 microns wide, and the second width is less than 0.1 microns.