METAL INTERCONNECT OF SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

• US 20130214411A1
• Filed: 10/24/2012
• Published: 08/22/2013
• Est. Priority Date: 02/16/2012
• Status: Abandoned Application

• Current Assignee: Korea Advanced Institute of Science and Technology
• Original Assignee: Korea Advanced Institute of Science and Technology
• Inventors: KIM, Young Hwan, KIM, Seong Il, KIM, Yong Tae, KIM, Chun Keun
• Application Number:
  US13/659,345
• Publication Number:
  US 20130214411A1
• Time in Patent Office: Days
• US Class Current: 257/741
• CPC Class Codes: H01L 21/76814 post-treatment or after-treatment, e.g. cleaning or removal of oxides on underlying conductors
• CPC Class Codes: H01L 21/76826 by contacting the layer with gases, liquids or plasmas
• CPC Class Codes: H01L 21/76831 in via holes or trenches, e.g. non-conductive sidewall liners
• CPC Class Codes: H01L 21/7684 Smoothing; Planarisation
• CPC Class Codes: H01L 21/76843 formed in openings in a dielectric
• CPC Class Codes: H01L 23/53238 Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 23/5329 Insulating materials
• CPC Class Codes: H01L 23/53295 Stacked insulating layers
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

Provided is a method of manufacturing a metal interconnect of a semiconductor device including: forming a interconnect hole by patterning an interlayer insulating film formed on a substrate; performing a nitriding treatment on a surface of the interlayer insulating film by injecting a gas including nitrogen into a deposition apparatus in which the substrate is disposed; forming a diffusion preventing film by injecting the gas including nitrogen and a metal source gas into the deposition apparatus together; filling the interconnect hole with a metal; and removing the metal formed on a part other than the interconnect hole by a chemical mechanical polishing (CMP) process. Accordingly, the mechanical strength of the interlayer insulating film is increased, thereby preventing scratches or defects that are generated during the chemical mechanical polishing process.

Claims

1. A method of manufacturing a metal interconnect of a semiconductor device comprising

forming a interconnect hole by patterning an interlayer insulating film formed on a substrate;

performing a nitriding treatment on a surface of the interlayer insulating film by injecting a gas including nitrogen into a deposition apparatus in which the substrate is disposed;

forming a diffusion preventing film by injecting the gas including nitrogen and a metal source gas into the deposition apparatus together;

filling the interconnect hole with a metal; and

removing the metal formed on a part other than the interconnect hole by a chemical mechanical polishing (CMP) process.

2. The method of manufacturing a metal interconnect of a semiconductor device according to claim 1,

wherein, in said performing of the nitriding treatment on the surface of the interlayer insulating film by injecting the gas including nitrogen, at least one gas of nitrogen (N₂), ammonia (NH₃), nitrogen monoxide (NO), and nitrogen dioxide (NO₂) is injected.

3. The method of manufacturing a metal interconnect of a semiconductor device according to claim 1,

wherein said performing of the nitriding treatment on the surface of the interlayer insulating film by injecting the gas including nitrogen further comprises applying pulse plasma power to an upper electrode and a lower electrode of the deposition apparatus.

4. The method of manufacturing a metal interconnect of a semiconductor device according to claim 3,

wherein a momentary peak voltage difference of the pulse plasma power is maintained in a range of 1 kV to 10 kV.

5. The method of manufacturing a metal interconnect of a semiconductor device according to claim 1,

wherein said performing of the nitriding treatment on the surface of the interlayer insulating film by injecting the gas including nitrogen further comprises performing a heat treatment on the surface of the substrate.

6. The method of manufacturing a metal interconnect of a semiconductor device according to claim 5,

wherein the surface of the substrate is subjected to the heat treatment at a temperature range of 100°

C. to 500°

C.

7. The method of manufacturing a metal interconnect of a semiconductor device according to claim 1,

wherein said filling of the interconnect hole with the metal further comprises:

depositing a metal seed layer on the diffusion preventing film; and

forming copper on the metal seed layer using an electroplating method.

8. The method of manufacturing a metal interconnect of a semiconductor device according to claim 1, further comprising:

forming a protective film on the metal interconnect after the CMP process.

9. The method of manufacturing a metal interconnect of a semiconductor device according to claim 1,

wherein said operations are repeated two or more times so as to form a multi-layer metal interconnect.

10. A metal interconnect of a semiconductor device comprising:

an interlayer insulating film in which a interconnect hole is formed;

a hardness controlled unit which is obtained by performing a nitriding treatment on a surface of the interlayer insulating film on an upper portion of the interlayer insulating film and in the vicinity of the interconnect hole;

a diffusion preventing film which is formed on the hardness controlled unit formed in the vicinity of the interconnect hole; and

a metal filled in the interconnect hole.

11. The metal interconnect of a semiconductor device according to claim 10,

wherein the metal includes copper (Cu).

12. The metal interconnect of a semiconductor device according to claim 10,

wherein the interlayer insulating film includes silicon dioxide (SiO₂).

13. The metal interconnect of a semiconductor device according to claim 12,

wherein the interlayer insulating film is made of one of tetraethoxysilicate (TEOS), high-density plasma oxide (HDP-Oxide), and borophosphosilicate glass (BPSG).

14. The metal interconnect of a semiconductor device according to claim 10,

wherein the hardness controlled unit includes silicon nitride (SiN_x) or silicon oxynitride (SiO_yN_z).

15. The metal interconnect of a semiconductor device according to claim 10,

wherein a nitrogen concentration of the hardness controlled unit is between about 1% to about 75%.

16. The metal interconnect of a semiconductor device according to claim 10,

wherein a dielectric constant of the hardness controlled unit is lower than that of the interlayer insulating film by about 5% to about 15%.

17. The metal interconnect of a semiconductor device according to claim 10,

wherein the diffusion preventing film includes one of tungsten nitride (WN), tantalum nitride (TaN), and titanium nitride (TiN).

18. The metal interconnect of a semiconductor device according to claim 10,

wherein the metal interconnect has a multi-layer structure.

19. The metal interconnect of a semiconductor device according to claim 10, further comprising a protective film formed on the metal.

20. The metal interconnect of a semiconductor device according to claim 19,

wherein the protective film includes silicon nitride (SiN_x).