Semiconductor Package Including an Organic Substrate and Interposer Having Through-Semiconductor Vias

• US 20130214426A1
• Filed: 10/31/2012
• Published: 08/22/2013
• Est. Priority Date: 02/21/2012
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Zhao, Sam Ziqun, Khan, Rezaur Rahman
• Granted Patent: US 8,587,132 B2
• Time in Patent Office: Days
• US Class Current: 257/774
• CPC Class Codes: H01L 21/4857 Multilayer substrates multilayer metallisation on monolayer substrate H01L21/4846
• CPC Class Codes: H01L 2224/1403 Bump connectors having different sizes, e.g. different diameters, heights or widths
• CPC Class Codes: H01L 2224/14181 On opposite sides of the body
• CPC Class Codes: H01L 2224/14183 On contiguous sides of the body
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16227 the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/16235 the bump connector connecting to a via metallisation of the item
• CPC Class Codes: H01L 2224/17181 On opposite sides of the body
• CPC Class Codes: H01L 2224/30183 On contiguous sides of the body
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/73253 Bump and layer connectors
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 2225/06572 Auxiliary carrier between devices, the carrier having an electrical connection structure
• CPC Class Codes: H01L 2225/1023 the support being an insulating substrate
• CPC Class Codes: H01L 2225/1058 Bump or bump-like electrical connections, e.g. balls, pillars, posts
• CPC Class Codes: H01L 23/14 characterised by the material or its electrical properties printed circuit boards H05K1/00
• CPC Class Codes: H01L 23/145 Organic substrates, e.g. plastic
• CPC Class Codes: H01L 23/147 Semiconductor insulating substrates semiconductor conductive substrates H01L23/4926
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/49506 : an insulative substrate being used as a diepad, e.g. ceramic, plastic H01L23/49531 takes precedence
• CPC Class Codes: H01L 23/49575 : Assemblies of semiconductor devices on lead frames
• CPC Class Codes: H01L 23/49816 : Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 23/49822 : Multilayer substrates multilayer metallisation on monolayer substrate H01L23/498
• CPC Class Codes: H01L 23/49827 : Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 23/49833 : the chip support structure consisting of a plurality of insulating substrates
• CPC Class Codes: H01L 23/5226 : Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 23/5384 : Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors H01L23/5383, H01L23/5385 take precedence; pins attached to insulating substrates H01L23/49811
• CPC Class Codes: H01L 23/5385 : Assembly of a plurality of insulating substrates
• CPC Class Codes: H01L 23/5389 : the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/17 : of a plurality of bump connectors
• CPC Class Codes: H01L 24/32 : of an individual layer connector
• CPC Class Codes: H01L 24/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 25/00 : Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereofdevices consisting of a plurality of solid state components formed in or on a common substrate H01L27/00; photovoltaic modules or arrays of photovoltaic cells H01L31/042 ; panels or arrays of photo electrochemical cells H01G9/2068
• CPC Class Codes: H01L 25/0655 : the devices being arranged next to each other
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/105 : the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/1515 : Shape
• CPC Class Codes: H01L 2924/15153 : the die mounting substrate comprising a recess for hosting the device
• CPC Class Codes: H01L 2924/15192 : Resurf arrangement of the internal vias
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/15321 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/15331 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 : Encapsulation

Abstract

The present application discloses various implementations of a semiconductor package including an organic substrate and one or more interposers having through-semiconductor vias (TSVs). Such a semiconductor package may include a contiguous organic substrate having a lower substrate segment including first and second pluralities of lower interconnect pads, the second plurality of lower interconnect pads being disposed in an opening of the lower substrate segment. The contiguous organic substrate may also include an upper substrate segment having an upper width and including first and second pluralities of upper interconnect pads. In addition, the semiconductor package may include at least one interposer having TSVs for electrically connecting the first and second pluralities of lower interconnect pads to the first and second pluralities of upper interconnect pads. The interposer has an interposer width less than the upper width of the upper substrate segment.

Claims

1. A semiconductor package comprising:

a contiguous organic substrate having a lower substrate segment including a first and a second plurality of lower interconnect pads, said second plurality of lower interconnect pads disposed in an opening of said lower substrate segment;

said contiguous organic substrate also including an upper substrate segment having an upper width and including a first and a second plurality of upper interconnect pads;

an interposer including through-semiconductor vias (TSVs) for electrically connecting said first and second plurality of lower interconnect pads to said first and second plurality of upper interconnect pads;

said interposer having an interposer width less than said upper width of said upper substrate segment.

2. The semiconductor package of claim 1, wherein said second plurality of lower interconnect pads are configured for use as contact pads for receiving a lower semiconductor die.

3. The semiconductor package of claim 2, further comprising said lower semiconductor die.

4. The semiconductor package of claim 1, wherein said upper substrate segment includes upper contact pads for receiving an upper semiconductor die, said upper contact pads being capable of connection to said first and second plurality of upper interconnect pads.

5. The semiconductor package of claim 4, further comprising said upper semiconductor die.

6. The semiconductor package of claim 1, wherein a minimum pad pitch of said upper substrate segment is less than a minimum pad pitch of said lower substrate segment.

7. The semiconductor package of claim 1, wherein said interposer comprises silicon.

8-20. -20. (canceled)

21. A semiconductor package comprising:

an organic substrate having a lower substrate segment including a first plurality of lower interconnect pads;

said organic substrate including an upper substrate segment having an upper width and including a first plurality of upper interconnect pads;

an interposer for electrically connecting said first plurality of lower interconnect pads to said first plurality of upper interconnect pads;

said interposer having an interposer width less than said upper width of said upper substrate segment.

22. The semiconductor package of claim 21, wherein a second plurality of lower interconnect pads are configured for use as contact pads for receiving a lower semiconductor die.

23. The semiconductor package of claim 22, further comprising said lower semiconductor die.

24. The semiconductor package of claim 21, wherein said upper substrate segment includes upper contact pads for receiving an upper semiconductor die.

25. The semiconductor package of claim 24, further comprising said upper semiconductor die.

26. The semiconductor package of claim 21, wherein a minimum pad pitch of said upper substrate segment is less than a minimum pad pitch of said lower substrate segment.

27. The semiconductor package of claim 21, wherein said interposer comprises silicon.

28. A semiconductor package comprising:

an organic substrate having a lower substrate segment including a first and a second plurality of lower interconnect pads;

said organic substrate including an upper substrate segment having an upper width and including a first and a second plurality of upper interconnect pads;

an interposer for electrically connecting said first and second plurality of lower interconnect pads to said first and second plurality of upper interconnect pads;

said interposer having an interposer width less than said upper width of said upper substrate segment.

29. The semiconductor package of claim 28, wherein said second plurality of lower interconnect pads are configured for use as contact pads for receiving a lower semiconductor die.

30. The semiconductor package of claim 29, further comprising said lower semiconductor die.

31. The semiconductor package of claim 28, wherein said upper substrate segment includes upper contact pads for receiving an upper semiconductor die.

32. The semiconductor package of claim 31, further comprising said upper semiconductor die.

33. The semiconductor package of claim 28, wherein a minimum pad pitch of said upper substrate segment is less than a minimum pad pitch of said lower substrate segment.