3D-IC DIFFERENTIAL SENSING AND CHARGE SHARING SCHEME

• US 20130214761A1
• Filed: 07/03/2012
• Published: 08/22/2013
• Est. Priority Date: 02/21/2012
• Status: Active Grant

• Current Assignee: National Tsing Hua University
• Original Assignee: Meng-Fan Chang, Tsung-Hsien Huang
• Inventors: Huang, Tsung-Hsien, CHANG, MENG-FAN
• Granted Patent: US 9,170,287 B2
• Time in Patent Office: Days
• US Class Current: 324/76.77
• CPC Class Codes: G01R 25/00 Arrangements for measuring phase angle between a voltage and a current or between voltages or currents
• CPC Class Codes: G01R 31/2853 Electrical testing of internal connections or -isolation, e.g. latch-up or chip-to-lead connections G01R31/31717 takes precedence; test of chip-to-PCB or lead-to-PCB connections G01R31/66

Abstract

The present invention discloses a 3D-IC differential sensing and charge sharing scheme which includes a plurality of TSVs including a first TSV and a second TSV. A tracking circuit is coupled to the first TSV. A sensing circuit is coupled to the second TSV and the tracking circuit. A plurality of equaling circuits are provided and wherein each of equaling circuit is configured and electrically connected between adjacent two equaling circuits. A clamping circuit is coupled to the first TSV.

Claims

1. A 3D-IC differential sensing and charge sharing scheme, comprising:

a plurality of high loading structures, including a first high loading structure a second high loading structure;

a tracking circuit coupled to said first high loading structure;

a sensing circuit coupled to said second high loading structure and said tracking circuit;

a plurality of equaling circuits, a first equaling circuit of said plurality of equaling circuits arranged between two high loading structures of said plurality of high loading structures adjacent said first equaling circuit and coupled thereof; and

a clamping circuit coupled to said first high loading structure.

2. The scheme of claim 1, wherein said plurality of high loading structures are a plurality of TSVs.

3. The scheme of claim 1, wherein said tracking circuit includes a pair of dummy bit line and at least one tracking unit, said at least one tracking unit including a plurality of MOS transistors.

4. The scheme of claim 1, wherein said sensing circuit includes a sense amplifier, a comparator or an operational amplifier.

5. The scheme of claim 1, wherein said clamping circuit includes two sense amplifiers, said two sense amplifiers including a first sense amplifier and a second sense amplifier.

6. The scheme of claim 5, wherein a third terminal of said first sense amplifier and said second sense amplifier is electrically connected to said first high loading structure, and a second terminal of said first sense amplifier electrically connected to a first terminal of said second sense amplifier.

7. A 3D-IC differential sensing and charge sharing scheme, comprising:

a high loading structure;

a sensing circuit, coupled to said high loading structure;

an equaling circuit, coupled to a positive input terminal and a negative input terminal of said sensing circuit, and coupled to said high loading structure; and

a capacitor, coupled to one terminal of said equaling circuit and said negative input terminal of said sensing circuit for storing charge.

8. The scheme of claim 7, wherein said high loading structures is a TSV.

9. The scheme of claim 7, wherein said sensing circuit includes a sense amplifier, a comparator or an operational amplifier.

10. A method for charge-sharing of 3D-IC, comprising:

equaling all TSV signals;

opening a clamping circuit, and comparing a voltage of a first TSV of said all TSV;

if said voltage of said first TSV exceeds a specified range, then sending a pulse control signal for pre-charging to said first TSV, and thereby supplementing charge in a circuit to maintain a first voltage; and

opening a sensing circuit to output a sensing data or signal, and thereby determining a digital status as one or zero.

11. The method of claim 10, wherein said TSV signals include a differential tracking signal and a differential sensing signal.

12. The method of claim 10, further comprising clamping a lower level input signal to a pre-determined reference voltage level by said clamping circuit.