CIRCUIT FOR DETECTING A VOLTAGE CHANGE USING A TIME-TO-DIGITAL CONVERTER

• US 20130214831A1
• Filed: 02/21/2012
• Published: 08/22/2013
• Est. Priority Date: 02/21/2012
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Park, Sang Wook, Pedrali-Noy, Marzio, Raghunathan, Ashwin
• Granted Patent: US 8,669,794 B2
• Time in Patent Office: Days
• US Class Current: 327/156
• CPC Class Codes: G01R 19/255 using analogue/digital converters of the type with counting of pulses during a period of time proportional to voltage or current, delivered by a pulse generator with fixed frequency
• CPC Class Codes: G04F 10/005 Time-to-digital converters [TDC] analog-to-digital converters with intermediate conversion to time or phase H03M1/50, H03M1/60

Abstract

A circuit for detecting a voltage change is described. The circuit includes a supply insensitive pulse generator that generates a pulse signal. The circuit also includes a time-to-digital converter coupled to the supply insensitive pulse generator. The time-to-digital converter generates a digital signal based on the pulse signal and a voltage. The circuit also includes a controller coupled to the time-to-digital converter that detects a voltage change based on the digital signal.

Claims

1. A circuit for detecting a voltage change, comprising:

a supply insensitive pulse generator that generates a pulse signal;

a time-to-digital converter coupled to the supply insensitive pulse generator, wherein the time-to-digital converter generates a digital signal based on the pulse signal and a voltage; and

a controller coupled to the time-to-digital converter that detects a voltage change based on the digital signal.

2. The circuit of claim 1, wherein the controller generates a droop code only when the voltage change is a voltage drop.

3. The circuit of claim 2, wherein the controller resets the droop code if no additional voltage drop occurs within a period.

4. The circuit of claim 1, wherein the controller is coupled to a phase-locked loop that generates a clock signal for a processor, and wherein the controller adjusts a frequency of the clock signal based on the voltage change.

5. The circuit of claim 4, wherein the controller adjusts the frequency of the clock signal by switching off an injection signal from a slave voltage-controlled oscillator and adjusting a variable current source.

6. The circuit of claim 1, wherein the controller generates a calibration code to adjust the pulse signal from the supply insensitive pulse generator.

7. The circuit of claim 6, wherein the controller generates the calibration code by incrementing the calibration code until the digital signal is within a range.

8. The circuit of claim 1, wherein the supply insensitive pulse generator generates the pulse signal based on a frequency-divided clock signal.

9. The circuit of claim 1, wherein the digital signal comprises a thermometer code.

10. The circuit of claim 9, wherein the controller comprises a decoder that decodes the thermometer code into a 4-bit number.

11. A method for detecting a voltage change by a circuit, comprising:

generating a pulse signal by a supply insensitive pulse generator;

generating a digital signal by a time-to-digital converter based on the pulse signal and a voltage; and

detecting a voltage change based on the digital signal.

12. The method of claim 11, further comprising generating a droop code only when the voltage change is a voltage drop.

13. The method of claim 12, further comprising resetting the droop code if no additional voltage drop occurs within a period.

14. The method of claim 11, further comprising adjusting a frequency of a clock signal for a processor based on the voltage change.

15. The method of claim 14, wherein adjusting the frequency of the clock signal comprises switching off an injection signal from a slave voltage-controlled oscillator and adjusting a variable current source.

16. The method of claim 11, further comprising generating a calibration code to adjust the pulse signal from the supply insensitive pulse generator.

17. The method of claim 16, wherein generating the calibration code comprises incrementing the calibration code until the digital signal is within a range.

18. The method of claim 11, wherein the pulse signal is generated based on a frequency-divided clock signal.

19. The method of claim 11, wherein the digital signal comprises a thermometer code.

20. The method of claim 19, further comprising decoding the thermometer code into a 4-bit number.

21. A computer-program product for detecting a voltage change, comprising a non-transitory tangible computer-readable medium having instructions thereon, the instructions comprising:

code for causing a circuit to generate a pulse signal by a supply insensitive pulse generator;

code for causing the circuit to generate a digital signal by a time-to-digital converter based on the pulse signal and a voltage; and

code for causing the circuit to detect a voltage change based on the digital signal.

22. The computer-program product of claim 21, the instructions further comprising code for causing the circuit to generate a droop code only when the voltage change is a voltage drop.

23. The computer-program product of claim 22, the instructions further comprising code for causing the circuit to reset the droop code if no additional voltage drop occurs within a period.

24. The computer-program product of claim 21, the instructions further comprising code for causing the circuit to adjust a frequency of a clock signal for a processor based on the voltage change.

25. The computer-program product of claim 21, the instructions further comprising code for causing the circuit to generate a calibration code to adjust the pulse signal from the supply insensitive pulse generator.

26. An apparatus for detecting a voltage change, comprising:

means for generating a pulse signal that is insensitive to variations in supply voltage;

means for generating a digital signal based on the pulse signal and a voltage; and

means for detecting a voltage change based on the digital signal.

27. The apparatus of claim 26, further comprising means for generating a droop code only when the voltage change is a voltage drop.

28. The apparatus of claim 27, further comprising means for resetting the droop code if no additional voltage drop occurs within a period.

29. The apparatus of claim 26, further comprising means for adjusting a frequency of a clock signal for a processor based on the voltage change.

30. The apparatus of claim 26, further comprising means for generating a calibration code to adjust the pulse signal.