High Current, Low Equivalent Series Resistance Printed Circuit Board Coil for Power Transfer Application

• US 20130214890A1
• Filed: 06/27/2012
• Published: 08/22/2013
• Est. Priority Date: 02/20/2012
• Status: Abandoned Application

• Current Assignee: Futurewei Technologies Incorporated (Huawei Investment & Holding Co., Ltd.)
• Original Assignee: Futurewei Technologies Incorporated (Huawei Investment & Holding Co., Ltd.)
• Inventors: Zabaco, Jorge
• Application Number:
  US13/535,059
• Publication Number:
  US 20130214890A1
• Time in Patent Office: Days
• US Class Current: 336/200
• CPC Class Codes: H01F 17/0013 with stacked layers
• CPC Class Codes: H01F 2017/002 Details of via holes for interconnecting the layers
• CPC Class Codes: H01F 2027/2809 on stacked layers
• CPC Class Codes: H01F 27/2804 Printed windings
• CPC Class Codes: H01F 38/14 Inductive couplings for wireless supply or distribution of electric power using inductive coupling H02J50/10
• CPC Class Codes: H01F 41/041 Printed circuit coils apparatus or processes for manufacturing printed circuits in general H05K3/00
• CPC Class Codes: H02J 50/12 of the resonant type
• CPC Class Codes: H04B 5/79 for data transfer in combination with power transfer
• CPC Class Codes: Y10T 29/4902 Electromagnet, transformer or inductor

Abstract

A method for fabricating an electric coil on a circuit board comprising fabricating on the circuit board a first coil layer comprising a coil trace and a plurality of vias distributed along the length of the coil trace, and overlaying a second coil layer on the first coil layer, wherein the vias of the first coil layer join the first coil layer and the second coil layer.

Claims

1. A method for fabricating an electric coil on a circuit board comprising:

fabricating on the circuit board a first coil layer comprising a coil trace and a plurality of vias distributed along the length of the coil trace; and

overlaying a second coil layer on the first coil layer,

wherein the vias of the first coil layer join the first coil layer and the second coil layer.

2. The method of claim 1, wherein the vias are distributed substantially across the entire coil trace to achieve higher current capability, lower equivalent series resistance (ESR), or both for the electric coil.

3. The method of claim 1, wherein the first coil layer and the second coil layer are overlaid on the circuit board, and wherein additional circuit components are integrated, overlaid, or both with the first coil layer and the second coil layer on the circuit board.

4. The method of claim 1, wherein the second coil layer comprises a second coil trace and a plurality of second vias.

5. The method of claim 4, wherein the second vias join the second coil trace to the coil trace, the vias, or both.

6. The method of claim 4 further comprising overlaying a third coil layer on the second coil layer, wherein the second vias of the second coil layer join the second coil layer and the third coil layer.

7. The method of claim 4, wherein the second coil trace mirrors the coil trace.

8. The method of claim 1 further comprising overlaying one or more additional coil layers on the first coil layer and the second coil layer to meet current capability, equivalent series resistance (ESR), or both requirements for the electric coil.

9. A method for reducing an overall thickness of a multilayer coil for wireless electrical power transfer, comprising:

fabricating a first coil layer comprising a first winding trace;

overlaying and distributing a plurality of vias across the first coil layer; and

overlaying on the vias a second coil layer comprising a second winding trace substantially similar to the winding trace, wherein the spaces between the vias are determined to increase the vias coverage of the surfaces of the first coil layer and the second coil layer.

10. The method of claim 9, wherein the vias between the first coil layer and the second coil layer are distributed substantially evenly across the surfaces of the first coil layer and the second coil layer.

11. The method of claim 9 further comprising:

overlaying and distributing a plurality of second vias across the second coil layer and

overlaying on the second vias a third coil layer comprising a third winding trace substantially similar to the winding trace, wherein the spaces between the second vias are reduced to increase the second vias coverage of the surfaces of the second coil layer and the third coil layer.

12. The method of claim 11, wherein the vias between the first coil layer and the second coil layer and the second vias between the second coil layer and the third coil layer are distributed similarly or differently to increase overall current flow and series resistance in the multilayer coil.

13. The method of claim 9, wherein the vias are overlaid across substantially the entire surfaces of the first coil layer and the second coil layer to increase current flow between the first coil layer and the second coil layer, reduce equivalent series resistance (ESR), and increase power transfer in comparison to overlaying fewer vias at some portions of the surfaces of the first coil layer and the second coil layer.

14. The method of claim 9, wherein the first coil layer and the second coil layer have a thickness determined to meet a desired equivalent series resistance (ESR) for the multilayer coil and to allow using the multilayer coil for a wireless charging component in a relatively thin handheld device.

15. The method of claim 9, wherein the vias are fabricated by patterning the vias on the first coil layer using lithography and then etching.

16. The method of claim 9, wherein the spaces between the vias are reduced as much as allowed by the PCB fabrication to increase the surface coverage of the first coil layer and the second coil layer by the vias.

17. The method of claim 9, wherein the vias have about the same size, surface, and dimensions that are designed to determine a quantity of vias that cover the surfaces of the first coil layer and the second coil layer.

18. The method of claim 9, wherein at least some of the vias have different sizes that are determined to increase current flow and series resistance in the multilayer coil.

19. An apparatus for a multilayer printed circuit board (PCB) coil, comprising:

a first coil layer of a PCB;

a plurality of vias coupled to and distributed to cover substantially the surface of the first coil layer within the PCB; and

a second coil layer of the PCB and coupled to the vias to cover substantially the surface of the second coil layer,

wherein the vias are positioned between the first coil layer and the second coil layer and enable substantially high current and low equivalent series resistance (ESR) for the multilayer PCB coil.

20. The apparatus of claim 19 further comprising one or more other circuit components integrated with the first coil layer and the second coil layer on the PCB.

21. The apparatus of claim 19, wherein the multilayer PCB coil is a component used in a wireless charging device.

22. The apparatus of claim 19, wherein the multilayer PCB coil is a component used in a near-field transmission device.

23. The apparatus of claim 19, wherein the vias have a cylindrical shape and are vertical with respect to the surfaces of the first coil layer and the second coil layer.