RESISTANCE CHANGE MEMORY CELL CIRCUITS AND METHODS
First Claim
1. A method of changing a state of a resistive change memory element of an integrated circuit device, the method comprising:
- generating a reference current;
biasing an access transistor coupled to the resistive change memory element to establish a bias of the access transistor; and
,based on the bias of the access transistor, using a current mirror to establish from the reference current, a current that flows through the resistive change memory element.
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Accused Products
Abstract
The gate of the access transistor of a 1 transistor 1 resistor (1T1R) type RRAM cell is biased relative to the source of the access transistor using a current mirror. Under the influence of a voltage applied across the 1T1R cell (e.g., via the bit line), the RRAM memory element switches from a higher resistance to a lower resistance. As the RRAM memory element switches from the higher resistance to the lower resistance, the current through the RRAM cell switches from being substantially determined by the higher resistance of the RRAM device (while the access transistor is operating in the linear region) to being substantially determined by the saturation region operating point of the access transistor.
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Citations
21 Claims
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1. A method of changing a state of a resistive change memory element of an integrated circuit device, the method comprising:
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generating a reference current; biasing an access transistor coupled to the resistive change memory element to establish a bias of the access transistor; and
,based on the bias of the access transistor, using a current mirror to establish from the reference current, a current that flows through the resistive change memory element. - View Dependent Claims (2, 3, 4, 5, 6)
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7. A method of performing a memory operation in an integrated circuit memory device to change a state of a resistive change memory element in an array having a plurality of bit lines and a plurality of word lines, comprising:
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providing a first voltage on a bit line of the plurality of bit lines to change a state of a resistive change memory cell; and
,providing a second voltage on a word line of the plurality of word lines, the second voltage to bias an access transistor using a current mirror to establish, from a reference current a current that flows through the resistive change memory element. - View Dependent Claims (8, 9, 10, 11, 12, 13, 14)
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15. An integrated circuit, comprising:
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at least one memory cell having an access transistor coupled to a resistive change memory element; a reference current generator; and
,a word line driver circuit to receive a reference current from the reference current generator, to generate a bias, and to bias the access transistor such that the reference current is mirrored as a current that flows through the access transistor. - View Dependent Claims (16, 17, 18, 19, 20)
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21-36. -36. (canceled)
Specification