MANAGING MEMORY SYSTEMS CONTAINING COMPONENTS WITH ASYMMETRIC CHARACTERISTICS

• US 20130219112A1
• Filed: 03/25/2013
• Published: 08/22/2013
• Est. Priority Date: 10/19/2007
• Status: Active Grant

• Current Assignee: Western Digital Technologies Incorporated (Western Digital Corporation)
• Original Assignee: Virident Systems Inc. (Western Digital Corporation)
• Inventors: Okin, Kenneth A., Karamcheti, Vijay
• Granted Patent: US 9,514,038 B2
• Time in Patent Office: Days
• US Class Current: 711/103
• CPC Class Codes: G06F 11/1658 Data re-synchronization of a redundant component, or initial sync of replacement, additional or spare unit
• CPC Class Codes: G06F 11/20 using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
• CPC Class Codes: G06F 12/02 Addressing or allocation; Relocation program address sequencing G06F9/00; arrangements for selecting an address in a digital store G11C8/00
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 12/06 Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication G06F12/08 takes precedence
• CPC Class Codes: G06F 12/08 in hierarchically structured memory systems, e.g. virtual memory systems
• CPC Class Codes: G06F 12/10 Address translation
• CPC Class Codes: G06F 2212/1032 Reliability improvement, data loss prevention, degraded operation etc
• CPC Class Codes: G06F 2212/205 Hybrid memory, e.g. using both volatile and non-volatile memory
• CPC Class Codes: G06F 2212/7201 Logical to physical mapping or translation of blocks or pages
• CPC Class Codes: G06F 2212/7202 Allocation control and policies
• CPC Class Codes: G11C 16/3418 Disturbance prevention or evaluation; Refreshing of disturbed memory data
• CPC Class Codes: G11C 16/3427 Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written

Abstract

A memory controller (MC) is associated with a remapping table to enable access to content in a memory system that includes asymmetric memory. The MC receives a request for a memory read or an Input/Output (I/O) write from a central processing unit (CPU) for a physical address specified by the system'"'"'s memory management unit (MMU). The CPU uses the MMU to manage memory operations for the CPU, by translating the virtual addresses associated with CPU instructions into physical addresses representing system memory or I/O locations. The MC for asymmetric memories is configured to process the MMU-specified physical addresses as an additional type of virtual addresses, creating a layer of abstraction between the physical address specified by the MMU and the physical memory address with which that address is associated by the MC. The MC shields the CPU from the computational complexities required to implement a memory system with asymmetric components.

Claims

1. A method comprising:

receiving, at a memory controller, a request for a write to a first address;

accessing remapping data associated with the memory controller;

using the remapping data to remap the first address to a first location within a storage unit, the first location within the storage unit being different than the first address;

identifying a first disruption region within the storage unit that includes the first location;

writing content from the first disruption region to a second disruption region;

processing, by the memory controller and during the writing of the content from the first disruption region to the second disruption region, read operations from the first disruption region;

determining that the content from the first disruption region has been written to the second disruption region; and

configuring the remapping data to associate the first address with a second location within the storage unit that corresponds to the second disruption region based on determining that the content from the first disruption region has been written to the second disruption region.

2. The method of claim 1 wherein the first disruption region and the second disruption region include physical addresses that are associated with characteristics that include corrupted content or nondeterministic read latency as a result of processing read operations from the first disruption region concurrent with the writing of the content from the first disruption region to the second disruption region.

3. The method of claim 1 further comprising processing, by the memory controller, write operations to write to the second disruption region until a prior write operation has been completed.

4. The method of claim 1 further comprising leveraging the memory controller to align the first disruption region and the second disruption region including:

after the content in the first disruption region has been written to the second disruption region, using the memory controller to write data newly-written to the second disruption region and distinct of data within the first disruption region to the first disruption region, and

using the memory controller to process read operations, as data from the second disruption region is being written to the first disruption region, from the second disruption region until the data has been written to the first disruption region.

5. The method of claim 1 further comprising leveraging the memory controller to align the first disruption region and the second disruption region so that transferring data between the first disruption region and the second disruption region only reflects content that has been updated.

6. The method of claim 1 further comprising:

receiving, at the memory controller, a write instruction related to data that resides in the first disruption region;

queuing the write instruction until the content has been written to the second disruption region; and

executing the write instruction in response to determining that the content has been written to the second disruption region.

7. The method of claim 1 further comprising:

exchanging, using the memory controller and across an interconnection, physical address information for a memory system including the storage unit; and

automatically loading requested data, using the physical address information across the interconnection, in response to receiving a read instruction.

8. The method of claim 1 wherein receiving, at the memory controller, the request for a write to a first address includes:

receiving a request for an I/O write on a Dual Inline Memory Module (DIMM); and

routing the request for the I/O write to a memory controller embedded within the DIMM.

9. The method of claim 1 wherein identifying the first disruption region includes identifying multiple areas of organized memory across multiple areas on a single device.

10. The method of claim 1 wherein identifying the first disruption region includes identifying multiple areas on multiple devices that are organized around a memory controller-specified physical address in the remapping data.

11. The method of claim 1 wherein accessing the remapping data associated with the memory controller includes:

accessing a read translation table that is physically coupled to the storage unit, and

accessing a write translation table that is physically coupled to the storage unit.

12. The method of claim 1 wherein accessing the remapping data associated with the memory controller includes:

accessing a read translation table that is physically coupled to the storage unit, and

accessing a write translation table that is stored in a different location than the read location table.

13. The method of claim 1 wherein accessing the remapping data associated with the memory controller includes accessing remapping data that is embedded as a DIMM-based memory controller.

14. The method of claim 1 wherein accessing the remapping data associated with the memory controller includes accessing several divided tables, where each of the divided tables are associated with two or more disruption regions within a DIMM.

15. The method of claim 1 further comprising configuring the memory controller to interface with symmetric memory and asymmetric memory, wherein the storage unit is part of the asymmetric memory.

16. The method of claim 1 further comprising configuring the memory controller to interface with only asymmetric memory, wherein the storage unit is part of the asymmetric memory.

17. The method of claim 1 further comprising configuring the memory controller to operate in a distributed mode, wherein the memory controller is configured to:

perform read translations using memory controller logic, and

perform write operations using a portion of the remapping data implemented as a software-managed table residing with an application, a hypervisor, an operating system, a CPU, or a memory controller.

18. The method of claim 1 wherein the storage unit includes NOR flash memory.

19. The method of claim 1 wherein the storage unit includes phase change memory.

20. The method of claim 1 wherein the first disruption region includes a first bank within NOR flash memory and the second disruption region includes a second bank within the NOR flash memory, and wherein identifying a first disruption region includes identifying the first bank within the NOR flash memory.