SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

• US 20130221347A1
• Filed: 02/26/2013
• Published: 08/29/2013
• Est. Priority Date: 02/29/2012
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Isobe, Atsuo, Tezuka, Sachiaki, Ohno, Shinji
• Granted Patent: US 9,553,200 B2
• Time in Patent Office: Days
• US Class Current: 257/43
• CPC Class Codes: H01L 21/02565 Oxide semiconducting materials not being Group 12/16 materials, e.g. ternary compounds
• CPC Class Codes: H01L 21/02595 polycrystalline
• CPC Class Codes: H01L 21/02631 Physical deposition at reduced pressure, e.g. MBE, sputtering, evaporation
• CPC Class Codes: H01L 29/04 characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes characterised by physical imperfections H01L29/30
• CPC Class Codes: H01L 29/24 including, apart from doping materials or other impurities, only semiconductor materials not provided for in groups H01L29/16, H01L29/18, H01L29/20, H01L29/22 including organic materials H10K99/00
• CPC Class Codes: H01L 29/66742 Thin film unipolar transistors
• CPC Class Codes: H01L 29/66969 of devices having semiconductor bodies not comprising group 14 or group 13/15 materials comprising selenium or tellurium in uncombined form other than as impurities in semiconductor bodies of other materials, comprising cuprous oxide or cuprous iodide H01L21/02365
• CPC Class Codes: H01L 29/78603 characterised by the insulating substrate or support H01L29/78657 takes precedence
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

Abstract

An oxide semiconductor layer is formed, a gate insulating layer is formed over the oxide semiconductor layer, a gate electrode layer is formed to overlap with the oxide semiconductor layer with the gate insulating layer interposed therebetween, a first insulating layer is formed to cover the gate insulating layer and the gate electrode layer, an impurity element is introduced through the insulating layer to form a pair of impurity regions in the oxide semiconductor layer, a second insulating layer is formed over the first insulating layer, the first insulating layer and the second insulating layer are anisotropically etched to form a sidewall insulating layer in contact with a side surface of the gate electrode layer, and a source electrode layer and a drain electrode layer in contact with the pair of impurity regions are formed.

Claims

1. A method for manufacturing a semiconductor device comprising the steps of:

forming an oxide semiconductor layer;

forming a gate insulating layer over the oxide semiconductor layer;

forming a gate electrode layer to overlap with the oxide semiconductor layer with the gate insulating layer interposed therebetween;

forming a first insulating layer to cover the gate insulating layer and the gate electrode layer;

introducing an impurity element through the first insulating layer to form a pair of impurity regions in the oxide semiconductor layer;

forming a second insulating layer over the first insulating layer;

etching the first insulating layer and the second insulating layer to form a sidewall insulating layer in contact with a side surface of the gate electrode layer;

forming a source electrode layer in contact with one of the pair of impurity regions; and

forming a drain electrode layer in contact with the other of the pair of impurity regions.

2. The method for manufacturing a semiconductor device according to claim 1, wherein the oxide semiconductor layer includes a microcrystal.

3. The method for manufacturing a semiconductor device according to claim 1, wherein the oxide semiconductor layer includes indium, gallium, and zinc.

4. The method for manufacturing a semiconductor device according to claim 1, wherein an oxide vacancy is formed in the pair of impurity regions.

5. The method for manufacturing a semiconductor device according to claim 1, wherein the sidewall insulating layer includes the impurity element.

6. The method for manufacturing a semiconductor device according to claim 1, wherein the sidewall insulating layer comprises the first insulating layer and the second insulating layer.

7. The method for manufacturing a semiconductor device according to claim 1, wherein a thickness of the second insulating layer is larger than a thickness of the first insulating layer.

8. A method for manufacturing a semiconductor device comprising the steps of:

forming an oxide semiconductor layer;

forming a gate insulating layer over the oxide semiconductor layer;

forming a gate electrode layer to overlap with the oxide semiconductor layer with the gate insulating layer interposed therebetween;

forming a first insulating layer to cover the gate insulating layer and the gate electrode layer;

introducing an impurity element through the first insulating layer to form a pair of impurity regions in the oxide semiconductor layer;

forming a second insulating layer over the first insulating layer;

etching the first insulating layer and the second insulating layer to form a sidewall insulating layer in contact with a side surface of the gate electrode layer;

forming a conductive layer to cover the oxide semiconductor layer, the sidewall insulating layer, and the gate electrode layer; and

removing a region of the conductive layer to form a source electrode layer and a drain electrode layer, wherein the region overlaps with the gate electrode layer.

9. The method for manufacturing a semiconductor device according to claim 8, wherein the oxide semiconductor layer includes a microcrystal.

10. The method for manufacturing a semiconductor device according to claim 8, wherein the oxide semiconductor layer includes indium, gallium, and zinc.

11. The method for manufacturing a semiconductor device according to claim 8, wherein an oxide vacancy is formed in the pair of impurity regions.

12. The method for manufacturing a semiconductor device according to claim 8, wherein the sidewall insulating layer includes the impurity element.

13. The method for manufacturing a semiconductor device according to claim 8, wherein the sidewall insulating layer comprises the first insulating layer and the second insulating layer.

14. The method for manufacturing a semiconductor device according to claim 8, wherein a thickness of the second insulating layer is larger than a thickness of the first insulating layer.

15. The method for manufacturing a semiconductor device according to claim 8, wherein a chemical mechanical polishing treatment is used to remove the conductive layer.

16. A semiconductor device comprising:

an oxide semiconductor layer, the oxide semiconductor layer including a pair of impurity regions containing an impurity element and a channel formation region between the pair of impurity regions;

a gate electrode layer over the oxide semiconductor layer;

a sidewall insulating layer being in contact with a side surface of the gate electrode layer and containing the impurity element;

a source electrode layer in contact with one of the pair of impurity regions; and

a drain electrode layer in contact with the other of the pair of impurity regions,

wherein in the pair of impurity regions, an impurity concentration in a region in contact with the source electrode layer or the drain electrode layer is higher than an impurity concentration in a region overlapping with the sidewall insulating layer.

17. The semiconductor device according to claim 16, wherein the oxide semiconductor layer includes a microcrystal.

18. The semiconductor device according to claim 16, wherein the oxide semiconductor layer includes indium, gallium, and zinc.

19. The semiconductor device according to claim 16, wherein an oxide vacancy is formed in the pair of impurity regions.

20. The semiconductor device according to claim 16, wherein the sidewall insulating layer includes the impurity element.

21. The semiconductor device according to claim 16, wherein a thickness of the second insulating layer is larger than a thickness of the first insulating layer.

22. The semiconductor device according to claim 16, further comprising a base insulating layer in contact with the oxide semiconductor layer,

wherein the base insulating layer includes a region containing oxygen in excess of a stoichiometric composition.