ARRAY SUBSTRATE AND MANUFACTURING METHOD THEREOF

• US 20130221357A1
• Filed: 08/22/2012
• Published: 08/29/2013
• Est. Priority Date: 08/23/2011
• Status: Active Grant

• Current Assignee: Beijing BOE Display Technology Co Ltd (BOE Technology Group Co., Ltd.), BOE Technology Group Co., Ltd.
• Original Assignee: Beijing BOE Display Technology Co Ltd (BOE Technology Group Co., Ltd.), BOE Technology Group Co., Ltd.
• Inventors: Wang, Dan, Shao, Xibin, Zhang, Honglin
• Granted Patent: US 9,070,772 B2
• Time in Patent Office: Days
• US Class Current: 257/59
• CPC Class Codes: G02F 1/1368 in which the switching element is a three-electrode device G02F1/136277 takes precedence
• CPC Class Codes: H01L 27/1288 employing particular masking sequences or specially adapted masks, e.g. half-tone mask
• CPC Class Codes: H01L 29/66477 with an insulated gate, i.e. MISFET
• CPC Class Codes: H01L 29/66765 Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate
• CPC Class Codes: H01L 29/786 Thin film transistors, i.e. transistors with a channel being at least partly a thin film transistors having only the source or the drain region on an insulator layer H01L29/0653; thin film FinFETs H01L29/785

Abstract

Embodiments of the present invention disclose an array substrate and a manufacturing method thereof. The method comprises forming a patterned active layer on a gate insulating layer, the active layer covering a part of the gate insulating layer; forming a source/drain electrode material layer on the active layer and the gate insulating layer; forming a patterned insulating layer on the source/drain electrode material layer; conducting an etching process by using the insulating layer as a mask, so as to etch the source/drain electrode material layer to form a source electrode and a drain electrode, etch a part of the insulating layer to form a via hole in the insulating layer over the drain electrode, and etch a part of the active layer between the source electrode and the drain electrode to form a channel.

Claims

1. A method for manufacturing an array substrate, comprising:

forming a patterned active layer on a gate insulating layer, the active layer covering a part of the gate insulating layer;

forming a source/drain electrode material layer on the active layer and the gate insulating layer;

forming a patterned insulating layer on the source/drain electrode material layer;

conducting an etching process by using the insulating layer as a mask, so as to etch the source/drain electrode material layer to form a source electrode and a drain electrode, etch a part of the insulating layer to form a via hole in the insulating layer over the drain electrode, and etch a part of the active layer between the source electrode and the drain electrode to form a channel.

2. The method according to claim 1, wherein the step of forming the patterned insulating layer comprises:

applying a layer of insulating material onto the source/drain electrode material layer;

patterning the layer of insulating material by using a half-tone mask process, so as to remove the layer of insulating material beyond a region for forming the source electrode and the drain electrode and expose the source/drain electrode material layer corresponding to a position of the channel, and remove a part of the layer of insulating material corresponding to a position of the via hole to form a recess in the layer of insulating material.

3. The method according to claim 2, wherein a part of the layer of insulating material remains in the recess, so that the source/drain electrode material layer underneath the recess is unexposed.

4. The method according to claim 3, wherein the step of conducting the etching process by using the insulating layer as the mask comprises:

etching the source/drain electrode material layer by using the patterned insulating layer as the mask to remove the source/drain electrode material layer beyond the region for forming the source electrode and the drain electrode, thereby forming the source electrode and the drain electrode and exposing the active layer corresponding to the position of the channel;

etching the insulating layer to thin the insulating layer and remove the remaining insulating layer in the recess, so as to form the via hole; and

simultaneously with etching the insulating layer, removing the part of the active layer corresponding to the position of the channel, so as to form the channel.

5. The method according to claim 4,

wherein the active layer comprises an amorphous silicon layer and a doped amorphous silicon layer on the amorphous silicon layer;

wherein, simultaneously with etching the insulating layer, the doped amorphous silicon layer is etched to expose the amorphous silicon layer.

6. The method according to claim 4, wherein the source/drain electrode material layer is etched by a wet-etching method, and the insulating layer is etched by a dry-etching method.

7. The method according to claim 3, wherein the thickness of the remaining insulating layer in the recess is smaller than half of an original thickness of the insulating layer.

8. The method according to claim 1, wherein, before forming the active layer, the method further comprises:

forming a common electrode and a gate electrode on a substrate; and

forming the gate insulating layer on the common electrode and the gate electrode to cover the common electrode and the gate electrode.

9. The method according to claim 8, wherein the patterned active layer is disposed over the gate electrode.

10. The method according to claim 1, further comprising:

forming a pixel electrode after forming the via hole, the pixel electrode being connected with the drain electrode through the via hole.

11. The method according to claim 1, further comprising:

forming an insulating protection layer after forming the pixel electrode, so as to cover the channel and a part of the insulating layer at both sides of the channel.

12. The method according to claim 1, wherein the step of forming the patterned active layer comprises:

applying a layer of material for forming the active layer onto the gate insulating layer; and

patterning the layer of material for forming the active layer to form the active layer.

13. The method according to claim 1, wherein an edge of the active layer is at he inner side of an edge of the source electrode and the drain electrode.

14. An array substrate, comprising:

a substrate;

a gate electrode and a common electrode disposed on the substrate;

a gate insulating layer covering the gate electrode and the common electrode;

an active layer disposed on the gate insulating layer and over the gate electrode;

a source electrode and a drain electrode disposed on the active layer, the source electrode and the drain electrode being separated from each other so as to form a channel in the active layer between the source electrode and the drain electrode, the channel being disposed over the gate electrode;

an insulating layer disposed over the source electrode and the drain electrode, the insulating layer having a via hole over the drain electrode; and

a pixel electrode connected with the drain electrode through the via hole,

wherein an edge of the active layer is at the inner side of an edge of the source electrode and the drain electrode.

15. The array substrate according to claim 14, wherein the edge of the insulating layer is substantially aligned with the edge of the source electrode and the drain electrode.

16. The array substrate according to claim 14, further comprising:

a protection layer disposed on the channel and a part of the insulating layer at both sides of the channel.