ELECTRONIC DEVICE INCLUDING A TRENCH AND A CONDUCTIVE STRUCTURE THEREIN AND A PROCESS OF FORMING THE SAME

• US 20130221436A1
• Filed: 02/24/2012
• Published: 08/29/2013
• Est. Priority Date: 02/24/2012
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Inventors: Hossain, Zia, Grivna, Gordon M.
• Granted Patent: US 9,070,585 B2
• Time in Patent Office: Days
• US Class Current: 257/334
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41741 for vertical or pseudo-vertical devices
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence

Abstract

An electronic device can include a transistor structure, including a patterned semiconductor layer overlying a substrate and having a primary surface. The electronic device can further include first conductive structures within each of a first trench and a second trench, a gate electrode within the first trench and electrically insulated from the first conductive structure, a first insulating member disposed between the gate electrode and the first conductive structure within the first trench, and a second conductive structure within the second trench. The second conductive structure can be electrically connected to the first conductive structures and is electrically insulated from the gate electrode. The electronic device can further include a second insulating member disposed between the second conductive structure and the first conductive structure within the second trench. Processing sequences can be used that simplify formation of the features within the electronic device.

Claims

1. An electronic device comprising a transistor structure, comprising:

a patterned semiconductor layer overlying a substrate and having a primary surface, wherein the patterned semiconductor layer defines a first trench and a second trench that extend from the primary surface towards the substrate;

first conductive structures within each of the first and second trenches;

a gate electrode within the first trench and electrically insulated from the first conductive structure;

a first insulating member disposed between the gate electrode and the first conductive structure within the first trench;

a second conductive structure within the second trench, wherein the second conductive structure is electrically connected to the first conductive structures and is electrically insulated from the gate electrode; and

a second insulating member disposed between the second conductive structure and the first conductive structure within the second trench.

2. The electronic device of claim 1, further comprising:

a source region within the patterned semiconductor layer, and wherein from a top view, the source region is disposed between the first and second trenches; and

a body contact region within the patterned semiconductor layer and between the first and second trenches.

3. The electronic device of claim 2, wherein the source region is disposed over substantially all of the body contact region.

4. The electronic device of claim 2, wherein the body contact region is disposed along a lateral surface of the second trench.

5. The electronic device of claim 1, further comprising:

other first trenches substantially identical to the first trench;

other gate electrodes within the other first trenches;

other second trenches substantially identical to the second trenches; and

other second conductive structures within the other second trenches,

wherein a ratio of a first number of gate electrodes to a second number of second conductive structures is in a range of approximately 0.75;

1 to approximately 1.5;

1.

6. The electronic device of claim 1, further comprising:

other first trenches substantially identical to the first trench;

other gate electrodes within the other first trenches;

other second trenches having different widths as compared to each other; and

other second conductive structures within the other second trenches,

wherein a ratio of a first number of gate electrodes to a second number of second conductive structures is in a range of approximately 0.75;

1 to approximately 1.5;

1.

7. The electronic device of claim 1, wherein in a direction substantially orthogonal to a channel length, the second conductive structure is wider than the first conductive structure within the second trench.

8. The electronic device of claim 1, wherein in a direction substantially orthogonal to a channel length, the second conductive structure is narrower than the first conductive structure within the second trench.

9. The electronic device of claim 1, wherein from a cross-sectional view, within the first and second trenches:

the first conductive structures have substantially a same composition and dimensions;

the first and second insulating members have substantially a same composition and dimensions;

the gate electrode and the second conductive structure have substantially a same composition;

bottom portions of the gate electrode and the second conductive structure have substantially identical bottom surfaces; and

an uppermost point of the gate electrode lies at a first elevation, and an uppermost point of the second conductive structure lies at a second elevation, wherein the primary surface generally corresponds to a third elevation that is closer to the first elevation than the second elevation.

10. A process of forming an electronic device comprising:

forming a semiconductor layer over a substrate, wherein the semiconductor layer has a primary surface;

patterning the semiconductor layer to define a first trench and a second trench that extend from the primary surface towards the substrate;

forming first conductive structures within the first and second trenches;

forming a first insulating member within the first trench after forming the first conductive structures;

forming a gate electrode within the first trench, wherein within the first trench, the first insulating member is disposed between the gate electrode and the first conductive structure;

forming a second insulating member within the second trench after forming the first conductive structures; and

forming a second conductive structure, wherein within the second trench, the second insulating member is disposed between the second conductive structure and the first conductive structure.

11. The process of claim 10, wherein forming the first insulating member and forming the second insulating member are performed substantially simultaneously.

12. The process of claim 10, further comprising:

forming an oxidation-resistant layer within the first and second trenches;

removing portions of the oxidation-resistant layer along bottoms of the first and second trenches to form an oxidation-resistant spacers; and

thermally oxidizing the semiconductor layer along bottoms of the first and second trenches while the oxidation-resistant spacers are within the first and second trenches,

wherein within a finished electronic device, oxide layers within the first and second trenches are thicker along between the first conductive structures and the bottoms of the first and second trenches as compared to the oxide layers between the first conductive structures and the sidewalls of the first and second trenches.

13. The process of claim 12, further comprising depositing a silicon layer within the first and second trenches after removing the portions of the oxidation-resistant layer and before forming the first conductive structures.

14. The process of claim 12, further comprising removing further portions of the oxidation-resistant spacers from within the first and second trenches at elevations above the first conductive structures, wherein remaining portions of the oxidation-resistant spacers are disposed between the first conductive structures and the sidewalls of the first and second trenches.

15. The process of claim 10, wherein forming the gate electrode and forming the second conductive structure comprise:

depositing a conductive layer within the first and second trenches after forming the first insulating member and forming the second insulating member;

removing portions of the conductive layer overlying the primary surface of the first and second trenches; and

recessing the conductive layer within the second trench such that substantially all of a remaining portion of the conductive layer within the second trench has an uppermost point that is below an elevation that generally corresponds to the primary surface.

16. The process of claim 10, wherein the gate electrode comprises a gate member that includes a narrower portion disposed within the first trench and a wider portion that lies at an elevation above the primary surface.

17. The process of claim 10, further comprising:

forming a body region within the semiconductor layer and adjacent to the first and second trenches;

forming a source region adjacent to the first trench after forming the gate electrode and before completing formation of the second conductive structure; and

forming a body contact region after completing formation of the second conductive structure.

18. The process of claim 17, wherein forming the body contact region comprises doping a portion of the semiconductor layer such that the body contact region is disposed along a lateral surface of the semiconductor layer.

19. The process of claim 17, wherein forming the body contact region comprises doping a portion of the semiconductor layer such that the body contact region is disposed along a vertical surface of the semiconductor layer and is spaced apart from a lateral surface of the semiconductor layer.

20. The process of claim 17, further comprising forming a conductive plug that is electrically connected to the source region, the body contact region, and the second conductive structure.