Semiconductor Device and Method of Forming Semiconductor Die with Active Region Responsive to External Stimulus

• US 20130221452A1
• Filed: 03/29/2013
• Published: 08/29/2013
• Est. Priority Date: 09/15/2011
• Status: Active Grant

• Current Assignee: Stats Chippac Pte. Ltd. (JCET Group Co., Ltd.)
• Original Assignee: Stats Chippac Limited
• Inventors: Han, Byung Joon, Shim, Il Kwon, Kuan, Heap Hoe, Strothmann, Thomas J., Anderson, Steve
• Granted Patent: US 9,553,162 B2
• Time in Patent Office: Days
• US Class Current: 257/414
• CPC Class Codes: H01L 21/56 Encapsulations, e.g. encapsulation layers, coatings
• CPC Class Codes: H01L 21/568 Temporary substrate used as encapsulation process aid H01L21/4832 and H01L21/566 take precedence
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/73209 Bump and HDI connectors
• CPC Class Codes: H01L 23/3128 the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 24/19 Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 24/20 Structure, shape, material or disposition of high density interconnect preforms
• CPC Class Codes: H01L 24/96 the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
• CPC Class Codes: H01L 24/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 27/14618 Containers
• CPC Class Codes: H01L 27/14683 Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof not peculiar thereto H01L21/00
• CPC Class Codes: H01L 29/66 Types of semiconductor device ; Multistep manufacturing processes therefor
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/01322 Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/12041 LED
• CPC Class Codes: H01L 2924/12042 LASER
• CPC Class Codes: H01L 2924/12043 Photo diode
• CPC Class Codes: H01L 2924/1306 Field-effect transistor [FET]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/1461 : MEMS
• CPC Class Codes: H01L 2924/181 : Encapsulation

Abstract

A semiconductor device has a semiconductor die and an encapsulant deposited over the semiconductor die. A conductive layer can be formed over the encapsulant and the semiconductor die. A transmissive layer can be formed over the semiconductor die. An interconnect structure can be formed through the encapsulant and electrically connected to the conductive layer, whereby the interconnect structure is formed off to only one side of the semiconductor die.

Claims

1. A method of making a semiconductor device, comprising:

providing a semiconductor die having an active region formed thereon;

depositing an encapsulant over the semiconductor die;

forming a conductive layer over the encapsulant and the semiconductor die;

forming a transmissive layer over the semiconductor die and the active region; and

forming a plurality of bumps through the encapsulant and electrically connected to the conductive layer, the plurality of bumps formed off to only one side of the semiconductor die.

2. The method of claim 1, wherein the active region is responsive to an external stimulus passing through the transmissive layer.

3. The method of claim 1, wherein the transmissive layer includes an optical dielectric material or an optical transparent or translucent material.

4. The method of claim 1, wherein the active region of the semiconductor die includes a sensor.

5. The method of claim 1, further including:

forming an insulating layer over the encapsulant;

forming an opening in the insulating layer over the plurality of bumps; and

depositing a conductive material in the opening.

6. The method of claim 5, further including:

forming external interconnects on the conductive material.

7. A method of making a semiconductor device, comprising:

providing a first semiconductor die having an active region formed thereon;

forming a first encapsulant around the first semiconductor die;

depositing a conductive layer over the first encapsulant and the first semiconductor die;

depositing a transmissive layer over the first semiconductor die including the active region;

forming a plurality of bumps through the first encapsulant and electrically connected to the conductive layer, the plurality of bumps formed on only one side of the first semiconductor die;

forming an opening in the transmissive layer over the active region of the first semiconductor die; and

disposing a second semiconductor die in the opening over the first semiconductor die.

8. The method of claim 7, further including:

forming a second encapsulant around the second semiconductor die; and

forming a second transmissive layer over the second semiconductor die.

9. The method of claim 8, wherein the second semiconductor die is a sensor responsive to an external stimulus passing through the second transmissive layer.

10. The method of claim 8, wherein the second transmissive layer includes an optical dielectric material or an optical transparent or translucent material.

11. A semiconductor device, comprising:

a first semiconductor die;

a first encapsulant deposited over the first semiconductor die;

a conductive layer formed over the first encapsulant and the first semiconductor die;

a first transmissive layer formed over the first semiconductor die; and

an interconnect structure formed through the first encapsulant and electrically connected to the conductive layer, wherein the interconnect structure is formed off to only one side of the first semiconductor die.

12. The device of claim 11, wherein the first transmissive layer includes an optical dielectric material or an optical transparent or translucent material.

13. The device of claim 11, wherein the first semiconductor die includes an active region responsive to an external stimulus passing through the first transmissive layer.

14. The device of claim 13, wherein the active region includes a sensor.

15. The device of claim 13, further including:

an insulating layer formed over the first encapsulant;

a first opening in the insulating layer over the interconnect structure; and

a conductive material deposited in the first opening.

16. The device of claim 15, further including:

external interconnects formed on the conductive material.

17. The device of claim 16, wherein the first transmissive layer includes a cavity over the active region of the first semiconductor die, and further including a second semiconductor die disposed in the cavity over the first semiconductor die.

18. The device of claim 17, further including a second encapsulant formed around the second semiconductor die, and a second transmissive layer formed over the second semiconductor die.

19. The device of claim 18, wherein the second transmissive layer includes an optical dielectric material or an optical transparent or translucent material.

20. The device of claim 19, wherein the second semiconductor die is a sensor responsive to an external stimulus passing through the second transmissive layer.