DISCRETE TIME ANALOG CIRCUIT AND RECEIVER USING SAME

• US 20130222164A1
• Filed: 07/27/2011
• Published: 08/29/2013
• Est. Priority Date: 07/28/2010
• Status: Active Grant

• Current Assignee: Panasonic Corporation (Panasonic Holdings Corporation)
• Original Assignee: Panasonic Corporation (Panasonic Holdings Corporation)
• Inventors: Araki, Kiyomichi, Morishita, Yohei, Shiozaki, Hiroka, Kanemaru, Masaki
• Granted Patent: US 8,766,834 B2
• Time in Patent Office: Days
• US Class Current: 341/122
• CPC Class Codes: H03H 15/00 Transversal filters electromechanical filters H03H9/46, H03H9/70
• CPC Class Codes: H03H 19/004 Switched capacitor networks
• CPC Class Codes: H03M 1/18 Automatic control for modifying the range of signals the converter can handle, e.g. gain ranging
• CPC Class Codes: H03M 1/50 with intermediate conversion to time interval H03M1/64 takes precedence

Abstract

The discrete time analog circuit (100) is provided with: a rotate capacitor circuit (150); an amplifier (141) that is connected to the input line or the output line of the rotate capacitor (150), and amplifies the input potential or input charge; a coefficient circuit (140) that is positioned in series with the amplifier (141), and has two history capacitors (143-1, 143-2) positioned parallel to each other; a first active capacitor among the two history capacitors (143-1, 143-2) that is connected to and charges the amplifier (141); and a clock generation circuit (110) that is connected to the input line or the output line without the involvement of the amplifier (141), and that sequentially changes the pairing of the rotate capacitor circuit (150) a second active capacitor, which shares a charge with the rotate capacitor circuit (150).

Claims

1. A discrete-time analog circuit comprising:

a rotating capacitor circuit;

at least one coefficient circuit including;

a potential holding section that amplifies input potential or input charge, the potential holding section connected to an input line of the rotating capacitor circuit; and

n charge holding sections disposed in series with the potential holding section and in parallel with each other, and

a circuit connection switching section that sequentially changes the pairing of a first charge holding section and a second charge holding section among the n charge holding sections, the first charge holding section being connected to the potential holding section and charged thereby, the second charge holding section being connected to the input line not via the potential holding section and sharing charge with the rotating capacitor circuit or being held at the potential at the rotating capacitor circuit.

2. The discrete-time analog circuit according to claim 1,

wherein the circuit connection switching section causes:

the first charge holding section at an i-th timing to be the second charge holding section at the i-th timing plus n−

1 timings; and

the second charge holding section at the i-th timing to be the first charge holding section at the i-th timing plus 1 timing.

5. The discrete-time analog circuit according to claim 2, further comprising:

a voltage-current converter that converts an input signal in the form of voltage into a signal in the form of current, the voltage-current converter being disposed at the input line of the rotating capacitor circuit;

a sampling switch that samples the current; and

a buffer capacitor disposed at an output line of the rotating capacitor circuit.

7. A discrete-time analog circuit comprising:

the discrete-time analog circuit according to claim 2 disposed at 1 to k locations;

a voltage-current converter that converts an input signal in the form of voltage into a signal in the form of current, the voltage-current converter being disposed at an input line of a first rotating capacitor circuit; and

a sampling switch that samples the current,

wherein an output line of a j-th (where j=1 to k−

1) rotating capacitor circuit is connected to an input line of a (j+1)-th rotating capacitor circuit, and

a buffer capacitor is connected to an output line of a k-th rotating capacitor circuit.

9. The discrete-time analog circuit according to claim 1,

wherein the rotating capacitor circuit includes two rotating capacitors and a circuit connection switching section, and

the circuit connection switching section alternately switches the two rotating capacitors between an input rotating capacitor and an output rotating capacitor, the input rotating capacitor being configured to be connected to the input line and the output rotating capacitor being configured to be connected to the output line.

10. The discrete-time analog circuit according to claim 1,

wherein the rotating capacitor circuit includes:

a potential holding section that amplifies input potential or input charge, the potential holding section being connected to the input line;

m charge holding sections disposed in series with the potential holding section and in parallel with each other; and

a circuit connection switching section that sequentially changes the pairing of a first charge holding section and a second charge holding section among the m charge holding sections, the first charge holding section being connected to the input line via the potential holding section and charged thereby, the second charge holding section being connected to an output line of the rotating capacitor circuit.

11. The discrete-time analog circuit according to claim 10,

wherein the circuit connection switching section causes:

the first charge holding section at an i-th timing to be the second charge holding section at the i-th timing plus m−

1 timing; and

the second charge holding section at the i-th timing to be the first charge holding section at the i-th timing plus 1 timing.

12. The discrete-time analog circuit according to claim 1,

wherein the rotating capacitor circuit includes:

m potential holding sections directly connected to the input line and disposed in parallel with each other; and

a circuit connection switching section that sequentially changes the pairing of a first charge holding section and a second charge holding section among the m charge holding sections, the first charge holding section being connected to the input line and charged thereby, the second charge holding section being connected to an output line of the rotating capacitor circuit.

13. The discrete-time analog circuit according to claim 12,

wherein the circuit connection switching section causes:

the first charge holding section at an i-th timing to be the second charge holding section at the i-th timing plus m−

1 timing, and

the second charge holding section at the i-th timing to be the first charge holding section at the i-th timing plus 1 timing.

14. The discrete-time analog circuit according to claim 1,

wherein the potential holding section is a source-grounded amplifier formed of a transistor, a bias circuit that appropriately biases the transistor, and a load resistor.

15. The discrete-time analog circuit according to claim 1,

wherein in the coefficient circuit or the rotating capacitor circuit, the potential holding section is formed of a voltage follower and the charge holding section is formed of M capacitors, and

the circuit connection switching section connects the M capacitors in parallel with each other at a timing when the M capacitors are connected to the voltage follower,

whereas the circuit connection switching section connects the M capacitors in series with each other at a timing when the M capacitors are connected to the input line not via the voltage follower.

16. The discrete-time analog circuit according to claim 1,

wherein the discrete-time analog circuit has a positive-phase system and an opposite-phase system, and

in at least one of the coefficient circuit and the rotating capacitor circuit,

a charge holding circuit connected to a positive-phase system at a timing when the charge holding circuit is connected to the potential holding circuit is connected to an opposite-phase system at a timing when the charge holding circuit is connected to the input line or an output line of the rotating capacitor circuit,

whereas the charge holding circuit connected to the opposite-phase system at the timing when the charge holding circuit is connected to the potential holding circuit is connected to the positive-phase system at the timing when the charge holding circuit is connected to the input line or the output line of the rotating capacitor circuit.

17. A receiver comprising:

the discrete-time analog circuit according to claim 1;

an antenna that receives an input signal;

a low noise amplifier that amplifies the signal received by the antenna and outputs the amplified signal to the discrete-time analog circuit; and

an analog-to-digital conversion section that converts an analog baseband signal outputted from the discrete-time analog circuit into a digital baseband signal and outputs the digital baseband signal.

3. A discrete-time analog circuit comprising:

a rotating capacitor circuit;

at least one coefficient circuit including;

a potential holding section that amplifies output potential or output charge, the potential holding section connected to an output line of the rotating capacitor circuit; and

n charge holding sections disposed in series with the potential holding section and in parallel with each other, and

a circuit connection switching section that sequentially changes the pairing of a first charge holding section and a second charge holding section among the n charge holding sections, the first charge holding section being connected to the potential holding section and charged thereby, the second charge holding section being connected to the output line not via the potential holding section and sharing charge with the rotating capacitor circuit or held at the potential at the rotating capacitor circuit.

4. The discrete-time analog circuit according to claim 3,

wherein the circuit connection switching section causes:

the first charge holding section at an i-th timing to be the second charge holding section at the i-th timing plus n−

1 timings, and

the second charge holding section at the i-th timing to be the first charge holding section at the i-th timing plus 1 timing.

6. The discrete-time analog circuit according to claim 4, further comprising:

a voltage-current converter that converts an input signal in the form of voltage into a signal in the form of current, the voltage-current converter being disposed at the input line of the rotating capacitor circuit;

a sampling switch that samples the current; and

a history capacitor.

8. A discrete-time analog circuit comprising:

the discrete-time analog circuit according to claim 4 disposed at 1 to k locations;

a voltage-current converter that converts an input signal in the form of voltage into a signal in the form of current, the voltage-current converter being disposed at an input line of a first rotating capacitor circuit;

a sampling switch that samples the current; and

a history capacitor,

wherein an output line of a j-th (where j=1 to k−

1) rotating capacitor circuit is connected to an input line of a (j+1)-th rotating capacitor circuit.

18. A receiver comprising:

the discrete-time analog circuit according to claim 3;

an antenna that receives an input signal;

a low noise amplifier that amplifies a signal received by the antenna and outputs the amplified signal to the discrete-time analog circuit; and

an analog-to-digital conversion section that converts an analog baseband signal outputted from the discrete-time analog circuit into a digital baseband signal and outputs the digital baseband signal.