NONVOLATILE MEMORY DEVICE AND EMBEDDED MEMORY SYSTEM INCLUDING THE SAME

• US 20130223148A1
• Filed: 01/28/2013
• Published: 08/29/2013
• Est. Priority Date: 02/28/2012
• Status: Abandoned Application

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Seo, BoYoung, Lee, YongKyu, Jeon, HeeSeog
• Application Number:
  US13/751,786
• Publication Number:
  US 20130223148A1
• Time in Patent Office: Days
• US Class Current: 365/185.11
• CPC Class Codes: G11C 16/0433 comprising cells containing a single floating gate transistor and one or more separate select transistors
• CPC Class Codes: G11C 16/14 Circuits for erasing electrically, e.g. erase voltage switching circuits
• CPC Class Codes: G11C 16/16 for erasing blocks, e.g. arrays, words, groups
• CPC Class Codes: H01L 27/04 the substrate being a semiconductor body
• CPC Class Codes: H01L 29/42328 with at least one additional gate other than the floating gate and the control gate, e.g. program gate, erase gate or select gate
• CPC Class Codes: H01L 29/7881 Programmable transistors with only two possible levels of programmation H01L29/7888 takes precedence
• CPC Class Codes: H01L 29/7883 charging by tunnelling of carriers, e.g. Fowler-Nordheim tunnelling
• CPC Class Codes: H10B 41/00 Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
• CPC Class Codes: H10B 41/30 characterised by the memory core region

Abstract

Integrated circuit memory devices include an array of nonvolatile memory cells having a plurality of pairs of nonvolatile memory cells therein. The plurality of pairs of nonvolatile memory cells include a first pair of nonvolatile memory cells, which share an erase gate electrode. Each of the nonvolatile memory cells in the first pair of nonvolatile memory cells includes a respective control gate electrode and the shared erase gate electrode extends between the control gate electrodes within the first pair of nonvolatile memory cells. Each of the first pair of nonvolatile memory cells may include a data storage transistor, which has a floating gate electrode therein, and a selection transistor. These transistors may be electrically connected in series and the shared erase gate electrode may extend between the floating gate electrodes.

Claims

1. An integrated circuit memory device, comprising:

an array of nonvolatile memory cells having a plurality of pairs of nonvolatile memory cells therein, said plurality of pairs of nonvolatile memory cells including a first pair of nonvolatile memory cells that share an erase gate electrode.

2. The memory device of claim 1, wherein each of the nonvolatile memory cells in the first pair of nonvolatile memory cells comprises a respective control gate electrode;

and wherein the shared erase gate electrode extends between the control gate electrodes within the first pair of nonvolatile memory cells.

3. The memory device of claim 2, wherein each of the first pair of nonvolatile memory cells comprises a data storage transistor having a floating gate electrode therein and a selection transistor.

4. The memory device of claim 3, wherein the selection transistor and the data storage transistor within one of the first pair of nonvolatile memory cells are electrically connected in series;

wherein a gate electrode of the selection transistor is electrically coupled to a respective word line; and

wherein each of the data storage transistors within the first pair of nonvolatile memory cells comprises a respective one of the control gate electrodes.

5. The memory device of claim 4, wherein the shared erase gate electrode extends between the floating gate electrodes within the first pair of nonvolatile memory cells.

6. The memory device of claim 5, further comprising control logic configured to support a page erase operation by applying unequal voltages to the control gate electrodes of the first pair of nonvolatile memory cells to thereby selectively erase one of the first pair of nonvolatile memory cells, but not the other.

7. The memory device of claim 2, further comprising control logic configured to support a page erase operation by applying unequal voltages to the control gate electrodes of the first pair of nonvolatile memory cells to thereby selectively erase one of the first pair of nonvolatile memory cells, but not the other.

8. A nonvolatile memory device, comprising:

a block of nonvolatile memory cells having a plurality of pairs of nonvolatile memory cells therein, said plurality of pairs of nonvolatile memory cells including first pair of nonvolatile memory cells that share a first erase gate electrode within a first sector of said block and a second pair of nonvolatile memory cells that share a second erase gate electrode within a second sector of said block;

a sector selecting circuit electrically connected to the first and second erase gate electrodes, an erase gate line and first and second sector selection lines; and

control logic electrically coupled to said erase gate line and the first and second sector selection lines, said control logic configured to support a multi-sector page erase operation by driving the first and second sector selection lines with signals that cause said sector selecting circuit to electrically connect the first and second erase gate electrodes to the erase gate line and further configured to support a single-sector page erase operation by driving the first and second sector selection lines with signals that cause said sector selecting circuit to electrically connect the erase gate line one-at-a-time to the first and second erase gate electrodes.

9. The memory device of claim 8, wherein said sector selecting circuit comprises first and second PMOS transistors having first and second gate electrodes, respectively, electrically connected to the first and second sector selection lines, respectively.

10. The memory device of claim 8, wherein each of the nonvolatile memory cells in the first pair of nonvolatile memory cells comprises a respective control gate electrode;

and wherein the shared first erase gate electrode extends between the control gate electrodes within the first pair of nonvolatile memory cells.

11. The memory device of claim 10, wherein each of the nonvolatile memory cells in the first pair of nonvolatile memory cells comprises a data storage transistor having a floating gate electrode therein and a selection transistor.

12. The memory device of claim 11, wherein the selection transistor and the data storage transistor within one of the first pair of nonvolatile memory cells are electrically connected in series;

wherein a gate electrode of the selection transistor is electrically coupled to a respective word line; and

wherein each of the data storage transistors within the first pair of nonvolatile memory cells comprises a respective one of the control gate electrodes.

13. A nonvolatile memory device comprising:

a memory cell array including a plurality of memory cells each having a cell transistor and a selection transistor, two adjacent memory cells of the plurality of memory cells sharing an erase gate; and

control logic configured to control the memory cell array;

wherein during an erase operation, the control logic applies different voltages to a control gate of a selected memory cell and a control gate of an unselected memory cell to perform an erase operation by a page unit.

14. The nonvolatile memory device of claim 13, wherein a first voltage is provided to the control gate of the selected memory cell, a second voltage higher than the first voltage is provided to the control gate of the unselected memory cell, and an erase voltage higher than the second voltage is provided to the erase gate.

15. The nonvolatile memory device of claim 14, wherein a potential difference between the first voltage and the erase voltage is larger than a predetermined potential different such that electrons are shifted into the erase gate from a floating gate of the selected memory cell.

16. The nonvolatile memory device of claim 14, wherein a potential difference between the second voltage and the erase voltage is smaller than a predetermined potential different such that electrons are shifted into the erase gate from a floating gate of the selected memory cell.

17. The nonvolatile memory device of claim 13, wherein the plurality of memory cells forms a first sector and a second sector, and the memory cell array further includes a sector selecting circuit placed between the first sector and the second sector.

18. The nonvolatile memory device of claim 17, wherein each of the first and second sectors includes at least two memory cells connected in series and an erase gate placed between the at least two memory cells, and the sector selecting circuit includes first and second transistors placed between an erase gate of the first sector and an erase gate of the second sector.

19. The nonvolatile memory device of claim 18, wherein the first transistor transfers an erase voltage to the erase gate of the first sector in response to a first sector selecting voltage, and the second transistor transfers the erase voltage to the erase gate of the second sector in response to a second sector selecting voltage, the first and second transistors being selectively turned on at an erase operation.

20. The nonvolatile memory device of claim 13, wherein the plurality of memory cells forms a first sector and a second sector, each of the first and second sectors includes at least two sub-sectors and an erase gate placed between the at least two sub-sectors, the at least two sub-sectors including at least two memory cells connected via the same word line and the same control gate line;

and

wherein the memory cell array further includes a selection circuit placed between the first sector and the second sector.

21-27. -27. (canceled)