METHOD FOR MAKING GATE-OXIDE WITH STEP-GRADED THICKNESS IN TRENCHED DMOS DEVICE FOR REDUCED GATE-TO-DRAIN CAPACITANCE

• US 20130224919A1
• Filed: 02/28/2012
• Published: 08/29/2013
• Est. Priority Date: 02/28/2012
• Status: Abandoned Application

• Current Assignee: Alpha & Omega Semiconductor, Ltd.
• Original Assignee: Alpha & Omega Semiconductor, Ltd.
• Inventors: Ding, Yongping, Lui, Sik, Bhalla, Anup
• Application Number:
  US13/406,814
• Publication Number:
  US 20130224919A1
• Time in Patent Office: Days
• US Class Current: 438/270
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/66719 With a step of forming an insulating sidewall spacer
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A method for making gate-oxide with step-graded thickness (S-G GOX) in a trenched DMOS device is proposed. First, a substrate is provided and a silicon oxide-silicon nitride-silicon oxide (ONO) protective composite layer is formed atop. Second, an upper interim trench (UIT), an upper trench protection wall (UTPW) and a lower interim trench (LIT) are created into the substrate. Third, the substrate material surrounding the LIT is shaped and oxidized into a desired thick-oxide-layer of thickness T1 and depth D1. Fourth, previously formed UTPW is stripped off from the device in progress, then a thin-gate-oxide of thickness T2 where T2<T1 is formed on the vertical surface of the UIT. Fifth, the UIT and LIT are filled with polysilicon then etched back into a polysilicon layer till its top surface defines a desired thin-gate-oxide depth D2.

Claims

1. A method for making gate-oxide with step-graded thickness (S-G GOX) in a trenched DMOS device supported on a substrate of a first conductivity type (N) for reduced gate-to-drain capacitance, expressed in X-Y-Z Cartesian coordinates with X-Y plane parallel to the major substrate plane and Z-axis pointing upwards, the trenched DMOS device comprising:

a drain of first conductivity type disposed at a bottom surface of the substrate;

a gate disposed in a trench opened from a top surface of the substrate, the gate having a polysilicon layer filling the trench padded by a gate-oxide layer with step-graded thickness (S-G GOX);

the S-G GOX includes a thick-oxide-layer of thickness T1 (X-Y plane), depth D1 (Z-axis) and covering a lower portion of the trench walls plus a thin-gate-oxide of thickness T2 (X-Y plane), depth D2 (Z-axis) and covering an upper portion of the trench walls with T2<

T1;

the method comprises;

a) providing the substrate and forming a silicon oxide-silicon nitride-silicon oxide (ONO) protective composite layer atop said substrate;

b) creating, into the substrate;

an upper interim trench (UIT) of cross sectional width Wa (X-Y plane) and depth Da (Z-axis) where Da>

D2;

an upper trench protection wall (UTPW) of thickness PWTK covering the vertical surfaces of the UIT, the UTPW itself being a bi-layer comprising a thin oxide of thickness T2′ and

a sacrificial nitride spacer layer (SNSL) of thickness SNTK such that T2′

+SNSL=PWTK; and

a lower interim trench (LIT), butted beneath the UIT, said LIT being of cross sectional width Wb and depth Db where Wb<

Wa, Wb=Wa−

2*PWTK and Db<

D1;

c) shaping and oxidizing the substrate material surrounding the LIT into the desired thick-oxide-layer of thickness T1, depth D1 and stripping off the SNSL and the thin oxide to expose the substrate material at the vertical surface of the UIT;

d) forming a thin-gate-oxide of thickness T2 on the vertical surfaces of the UIT; and

e) filling the UIT and LIT with polysilicon then etching it back into a polysilicon layer till its top surface defines the desired thin-gate-oxide depth D2.

2. The method of claim 1 wherein creating the UIT, the UTPW and the LIT comprise:

b1) masking, through a trench mask shaped according to the top cross sectional geometry (X-Y plane) of the trench;

b2) etching completely through the ONO composite layer followed by etching anisotropically but partially into the substrate to create the UIT;

b3) depositing the thin oxide atop the device in progress and forming the SNSL covering only the vertical surfaces of the UIT whereby completing the UTPW; and

b4) differentially etching away all the unprotected, by the SNSL and thin oxide, along the X-Y plane then anisotropically and partially etching into the substrate to complete the LIT.

3. The method of claim 2 wherein forming the SNSL covering only the vertical surfaces of the UIT comprises depositing a nitride spacer layer atop the device in progress then anisotropically etching away portions of the nitride spacer layer covering the horizontal surfaces of the thin oxide.

4. The method of claim 1 wherein shaping and oxidizing the substrate material comprise:

isotropically and partially etching the exposed substrate material surrounding the LIT to deepen the LIT with a rounded bottom floor; and

oxidizing the exposed substrate material surrounding the LIT, with a local oxidation of silicon LOCOS) process, into the desired thick-oxide-layer of thickness T1 and depth D1.

5. The method of claim 1 wherein providing the substrate comprises providing a substrate with a pre-formed drain layer of a first conductivity type (N) and a pre-formed uniform doping epitaxial layer of a first conductivity type (N) thereon, wherein the doping concentration of the drain layer is higher than that of the epitaxial layer.

6. The method of claim 1 further comprises:

e) forming body regions, source regions, device passivation regions and contact metallization atop the device in progress whereby completing the DMOS device.