HARDWIRED REMAPPED MEMORY

• US 20130227361A1
• Filed: 03/29/2013
• Published: 08/29/2013
• Est. Priority Date: 06/30/2009
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Bowers, Stephen, Billing, Gurkirat, Post, Samuel David
• Granted Patent: US 8,799,717 B2
• Time in Patent Office: Days
• US Class Current: 714/710
• CPC Class Codes: G06F 11/0727 in a storage system, e.g. in a DASD or network based storage system drivers for digital recording or reproducing units G06F3/06; circuits for error detection or correction within digital recording or reproducing units G11B20/18; for distributed storage of data in networks, e.g. transport arrangements for network file system [NFS], storage area networks [SAN] or network attached storage [NAS], H04L67/1097
• CPC Class Codes: G06F 11/073 in a memory management context, e.g. virtual memory or cache management memory management G06F12/00; testing of static memory units G11C29/00
• CPC Class Codes: G06F 11/076 by exceeding a count or rate limit, e.g. word- or bit count limit
• CPC Class Codes: G06F 11/0793 Remedial or corrective actions recovery from an exception in an instruction pipeline G06F9/3861; by retry G06F11/1402; for recovering from a failure of a protocol instance or entity H04L69/40
• CPC Class Codes: G06F 11/1448 Management of the data involved in backup or backup restore
• CPC Class Codes: G06F 11/1666 where the redundant component is memory or memory area
• CPC Class Codes: G06F 11/20 using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G11C 29/76 using address translation or modifications
• CPC Class Codes: G11C 29/82 for EEPROMs
• CPC Class Codes: G11C 29/846 by choosing redundant lines at an output stage

Abstract

Subject matter disclosed herein relates to on-the-fly remapping a memory device by hardware-switching data paths to locations of the memory device.

Claims

1. A system comprising:

a memory module comprising;

a main memory portion; and

a spare memory portion, wherein one or both of the main memory portion and the spare memory portion reside on multiple dies; and

a plurality of hardware switching components among the multiple dies, the plurality of hardware switching components being configured to redirect a data path of one or both of a data read process and a data write process to a spare memory portion location instead of a main memory portion location, the redirecting being based at least partially on a measure of bit errors generated by the main memory portion location.

2. The system of claim 1 further comprising:

a processor configured to process executable instructions for the one or both of the data read process and the data write process,

wherein the plurality of hardware switching components are configured to redirect the data path independently of the processor.

3. The system of claim 2, wherein the plurality of hardware switching components are configured to redirect the data path during processing of the executable instructions by the processor.

4. The system of claim 1, wherein the plurality of hardware switching components comprise multiplexers.

5. The system of claim 1, wherein at least one of the main memory portion location is a single memory cell and at least one of the spare memory portion location is another single memory cell.

6. The system of claim 1, wherein the main memory portion and/or the spare memory portion comprises phase change memory (PCM).

7. The system of claim 1 further comprising an error detection component configured to determine the measure of bit errors, the measure of bit errors comprising one or both of a bit error rate and a number of bit errors associated with read data from the main memory portion location.

8. The system of claim 1 further comprising a memory controller configured to perform a comparison of the measure of bit errors with an error threshold, and to determine whether to apply a redirect signal to one of the hardware switching components to redirect the data path to the spare memory portion location based on the comparison, wherein the memory controller is configured to apply the redirect signal if the measure of bit errors exceeds the error threshold.

9. The system of claim 8 further comprising an error correction component configured to correct bit errors generated by a memory portion location, wherein the error threshold comprises a level of bit errors exceeding an error correction threshold of the error correction component.

10. The system of claim 1, wherein the spare memory portion location is configured to replace the main memory portion location when the data path is redirected to the spare memory portion location such that a memory module comprising the main memory portion and the spare memory portion substantially maintains a constant memory capacity.

11. The system of claim 1 further comprising a register configured to store a signal associated with a memory selection value, the memory selection value being established based at least partially on a comparison of the measure of bit errors with an error threshold.

12. The system of claim 11, wherein the plurality of hardware switching components are further configured to redirect the data path based on the signal stored in the register.

13. The system of claim 1, wherein individual dies among the multiple dies each have a hardware switching component.

14. A method comprising:

receiving a signal representative of a command to read from or write to a main memory location of a main memory portion;

redirecting the signal representative of the command to a spare memory location of a spare memory portion, one or both of the main memory portion and the spare memory portion residing on multiple dies,

wherein the multiple dies have a plurality of hardware switching components configured to perform the redirecting, the redirecting being based at least partially on a measure of bit errors generated by the main memory location.

15. The method of claim 14, wherein one or both of the main memory portion and the spare memory portion comprise a phase change memory (PCM).

16. The method of claim 14 further comprising copying data from the main memory location to the spare memory location such that the spare memory location is configured to replace the main memory location.

17. The method of claim 14 further comprising operating a processor to initiate transmission of the signal representative of the command, wherein redirecting is performed independently of operating the processor.

18. The method of claim 14, wherein the measure of bit errors comprises one or both of a measure of a bit error rate and a number of bit errors generated by the main memory location.

19. The method of claim 14, further comprising providing, to an error detection component, read data from the main memory location to determine the measure of error bits.

20. The method of claim 14, further comprising:

associating a memory address of the command to read from or write to the main memory location with a memory selection value, the memory selection value being established based at least partially on a comparison of the measure of bit errors with an error threshold; and

providing the memory selection value to one of the hardware switching components for redirecting the signal representative of the command.