THIN FILM TRANSISTOR SUBSTRATE AND METHOD OF MANUFACTURING THE SAME

• US 20130228772A1
• Filed: 12/11/2012
• Published: 09/05/2013
• Est. Priority Date: 03/02/2012
• Status: Active Grant

• Current Assignee: Samsung Display Company Limited (Samsung Electronics Co. Ltd.)
• Original Assignee: Samsung Display Company Limited (Samsung Electronics Co. Ltd.)
• Inventors: KIM, Do-Hyun, MOH, Sang-Moon, CHOI, Youngjoo, KO, Gwang-Bum, RYU, GwonHeon, KIM, Joongeol, LEE, WooGeun, LEE, WONHEE
• Granted Patent: US 9,048,326 B2
• Time in Patent Office: Days
• US Class Current: 257/43
• CPC Class Codes: G02F 1/134363 for applying an electric field parallel to the substrate, i.e. in-plane switching [IPS]
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 27/1259 Multistep manufacturing methods
• CPC Class Codes: H01L 27/1288 employing particular masking sequences or specially adapted masks, e.g. half-tone mask
• CPC Class Codes: H01L 29/66969 of devices having semiconductor bodies not comprising group 14 or group 13/15 materials comprising selenium or tellurium in uncombined form other than as impurities in semiconductor bodies of other materials, comprising cuprous oxide or cuprous iodide H01L21/02365
• CPC Class Codes: H01L 29/78693 the semiconducting oxide being amorphous

Abstract

A thin film transistor substrate includes a substrate; a gate electrode on the substrate; a semiconductor pattern on the gate electrode; a source electrode on the semiconductor pattern; a drain electrode on the semiconductor pattern and spaced apart from the source electrode; a pixel electrode connected to the drain electrode; and a common electrode partially overlapped with the pixel electrode. The semiconductor pattern is in a same layer of the thin film transistor substrate as the pixel electrode and has an electrical property different from an electrical property of the pixel electrode.

Claims

1. A thin film transistor substrate comprising:

a substrate;

a gate electrode on the substrate;

a semiconductor pattern on the gate electrode;

a source electrode on the semiconductor pattern;

a drain electrode on the semiconductor pattern and spaced apart from the source electrode;

a pixel electrode connected to the drain electrode; and

a common electrode partially overlapped with the pixel electrode,

wherein the semiconductor pattern is in a same layer of the thin film transistor substrate as the pixel electrode and has an electrical property different from an electrical property of the pixel electrode.

2. The thin film transistor substrate of claim 1, wherein the pixel electrode has conductivity greater than conductivity of the semiconductor pattern.

3. The thin film transistor substrate of claim 2, wherein the pixel electrode is a conductor.

4. The thin film transistor substrate of claim 2, wherein the semiconductor pattern comprises a same material as the pixel electrode.

5. The thin film transistor substrate of claim 4, wherein the same material is amorphous indium-gallium-zinc-oxide.

6. The thin film transistor substrate of claim 1, wherein the pixel electrode is between a portion of the drain electrode and the substrate.

7. The thin film transistor substrate of claim 1, wherein the gate electrode overlaps edges of the semiconductor pattern in a plan view.

8. The thin film transistor substrate of claim 1, further comprising a common electrode line connected to the common electrode.

9. The thin film transistor substrate of claim 8, wherein the common electrode line is in a same layer of the thin film transistor substrate as the gate electrode.

10. The thin film transistor substrate of claim 1, wherein one of the pixel electrode and the common electrode comprises a plurality of slits.

11. The thin film transistor substrate of claim 1, further comprising:

a gate insulating layer between the gate electrode and the semiconductor pattern; and

an insulating layer between the pixel electrode and the common electrode.

12. A thin film transistor substrate comprising:

a substrate;

a gate electrode on the substrate;

a semiconductor pattern on the gate electrode;

a source electrode on the semiconductor pattern;

a drain electrode on the semiconductor pattern and spaced apart from the source electrode;

a pixel electrode connected to the drain electrode; and

a common electrode partially overlapped with the pixel electrode,

wherein the semiconductor pattern is in a same layer of the thin film transistor substrate as the common electrode and has an electrical property different from the common electrode.

13. A method of manufacturing a thin film transistor substrate, the method comprising:

preparing a substrate;

forming a gate electrode and a common electrode line on the substrate;

forming a semiconductor pattern layer comprising a first semiconductor pattern of which edges are overlapped by the gate electrode in a plan view, and a second semiconductor pattern spaced apart from the first semiconductor pattern;

irradiating an ultraviolet ray onto the semiconductor pattern layer through a rear surface of the substrate using the gate electrode as a mask, to form a pixel electrode;

forming a source electrode which contacts a first portion of the first semiconductor pattern;

forming a drain electrode which contacts with a second portion of the first semiconductor pattern and a portion of the pixel electrode, the drain electrode spaced apart from the source electrode; and

forming a common electrode partially overlapped with the pixel electrode.

14. The method of claim 13, further comprising forming an insulating layer to cover the gate electrode and the common electrode line, after the gate electrode and the common electrode line are formed.

15. The method of claim 14, wherein the forming the semiconductor pattern layer comprises:

depositing amorphous indium-gallium-zinc-oxide on the gate insulating layer; and

patterning the amorphous indium-gallium-zinc-oxide to form the first semiconductor pattern and the second semiconductor pattern.

16. The method of claim 15, wherein the first semiconductor pattern and the second semiconductor pattern are formed using a same mask.

17. The method of claim 13, wherein the pixel electrode is formed by irradiating the ultraviolet ray onto the second semiconductor pattern.

18. The method of claim 17, wherein the second semiconductor pattern has a conductor property by irradiating the ultraviolet ray thereto.

19. The method of claim 13, further comprising forming an insulating layer to cover the source electrode and the drain electrode, wherein the forming the insulating layer comprises:

depositing an insulating material over an entire surface of the substrate; and

patterning the insulating material to expose a portion of the common electrode line.

20. The method of claim 19, wherein the forming the common electrode comprises:

depositing a conductive material on the insulating layer; and

patterning the conductive material to form a plurality of slits.

21. A thin film transistor substrate comprising:

a substrate;

a gate electrode on the substrate;

a semiconductor pattern on the gate electrode;

a source electrode on the semiconductor pattern;

a drain electrode on the semiconductor pattern and spaced apart from the source electrode;

a pixel electrode connected to the drain electrode; and

a common electrode part partially overlapped with the pixel electrode and spaced apart from the semiconductor pattern,

wherein the semiconductor pattern is in a same layer of the thin film transistor substrate as the common electrode part, and the common electrode part comprises more layers than the semiconductor pattern.

22. The thin film transistor substrate of claim 21, wherein the common electrode part comprises a semiconductor layer and a conductive layer.

23. The thin film transistor substrate of claim 22, wherein the semiconductive layer is between the conductive layer and the substrate.

24. The thin film transistor substrate of claim 23, wherein the semiconductor pattern and the semiconductor layer of the common electrode part comprise amorphous indium-gallium-zinc-oxide.

25. The thin film transistor substrate of claim 24, wherein the conductive layer comprises gallium-zinc-oxide or zinc oxide.

26. The thin film transistor substrate of claim 21, further comprising:

a first insulating layer partially contacting with a portion of an upper surface of the semiconductor pattern; and

a second insulating layer on the first insulating layer, and between the common electrode part and the pixel electrode.

27. The thin film transistor substrate of claim 26, wherein a portion of the first insulating layer is between the source electrode and the drain electrode.

28. The thin film transistor substrate of claim 21, further comprising a common electrode line connected to the common electrode part.

29. The thin film transistor substrate of claim 28, wherein the common electrode line is in a same layer of the thin film transistor substrate as the gate electrode.

30. The thin film transistor substrate of claim 21, wherein one of the pixel electrode and the common electrode part comprises a plurality of slits.

31. A thin film transistor substrate comprising:

a substrate;

a gate electrode on the substrate;

a semiconductor pattern on the gate electrode;

a source electrode on the semiconductor pattern;

a drain electrode on the semiconductor pattern and spaced apart from the source electrode;

a pixel electrode part connected to the drain electrode and spaced apart from the semiconductor pattern; and

a common electrode partially overlapped with the pixel electrode part,

wherein the semiconductor pattern is in a same layer of the thin film transistor substrate as the pixel electrode part, and the pixel electrode part comprises more layers than the semiconductor pattern.

32. A method of manufacturing a thin film transistor substrate, comprising:

preparing a substrate;

forming a gate electrode and a common electrode line on the substrate;

forming a semiconductor pattern overlapped with the gate electrode, and a common electrode part spaced apart from the semiconductor pattern using a same mask;

depositing a first insulating material on the substrate including the semiconductor pattern and the common electrode part;

patterning the first insulating material to form a first insulating layer;

forming a source electrode which contacts a first portion of the semiconductor pattern;

forming a drain electrode which contacts a second portion of the semiconductor pattern, the drain electrode spaced apart from the source electrode; and

forming a pixel electrode partially overlapped with the common electrode part.

33. The method of claim 32, further comprising forming a gate insulating layer to cover the gate electrode and the common electrode line, after the gate electrode and the common electrode line are formed.

34. The method of claim 33, wherein the forming the semiconductor pattern and the common electrode part comprises:

depositing a semiconductor thin layer on the gate insulating layer;

depositing a conductive layer on the semiconductor layer; and

patterning the semiconductor thin layer and the conductive layer using the same mask, wherein the same mask is a slit mask or a diffraction mask.

35. The method of claim 34, wherein the patterning the semiconductor thin layer and the conductive layer comprises:

coating a photoresist on the semiconductor thin layer and the conductive layer;

exposing and developing the photoresist using the same mask, to form a first photoresist pattern;

etching the conductive layer and the semiconductor thin layer using the first photoresist pattern as a mask, to form a first pattern overlapped with the gate electrode, and a second pattern spaced apart from the first pattern;

etching a portion of the first photoresist pattern to form a second photoresist pattern; and

etching the conductive layer of the first pattern using the second photoresist pattern as a mask.

36. The method of claim 35, wherein the etching the conductive layer of the first pattern comprises using an etchant having a greater etch rate for the conductive layer than for the semiconductor thin layer.

37. The method of claim 35, wherein the second photoresist pattern exposes an upper surface of the first pattern and covers an upper surface of the second pattern.

38. The method of claim 37, wherein

the semiconductor thin layer comprises amorphous indium-gallium-zinc-oxide, and

the conductive layer comprises gallium-zinc-oxide or zinc oxide.

39. The method of claim 32, further comprising

depositing a second insulating material on the first insulating layer, the source electrode and the drain electrode, and

patterning the second insulating material to form a second insulating layer, after the source and drain electrodes are formed.

40. A method of manufacturing a thin film transistor substrate, comprising:

preparing a substrate;

forming a gate electrode and a common electrode line on the substrate;

forming a semiconductor pattern overlapped with the gate electrode, and a pixel electrode part spaced apart from the semiconductor pattern using one mask;

depositing a first insulating material on the substrate including the semiconductor pattern and the pixel electrode part;

patterning the first insulating material to form a first insulating layer;

forming a source electrode which contacts a first portion of the semiconductor pattern;

forming a drain electrode which contacts a second portion of the semiconductor pattern, the drain electrode spaced apart from the source electrode; and

forming a common electrode partially overlapped with the pixel electrode part.