HIGH VOLTAGE SEMICONDUCTOR DEVICES INCLUDING ELECTRIC ARC SUPPRESSION MATERIAL AND METHODS OF FORMING THE SAME

• US 20130228796A1
• Filed: 03/02/2012
• Published: 09/05/2013
• Est. Priority Date: 03/02/2012
• Status: Active Grant

• Current Assignee: CREE Incorporated (Wolfspeed, Inc.)
• Original Assignee: CREE Incorporated (Wolfspeed, Inc.)
• Inventors: Mieczkowski, Van
• Granted Patent: US 9,343,383 B2
• Time in Patent Office: Days
• US Class Current: 257/77
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/32245 the item being metallic
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/49171 Fan-out arrangements
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 23/047 the other leads being parallel to the base
• CPC Class Codes: H01L 23/20 gaseous at the normal operating temperature of the device
• CPC Class Codes: H01L 23/22 liquid at the normal operating temperature of the device
• CPC Class Codes: H01L 23/60 Protection against electrostatic charges or discharges, e.g. Faraday shields
• CPC Class Codes: H01L 24/32 of an individual layer connector
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/49 of a plurality of wire connectors
• CPC Class Codes: H01L 24/73 Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/10253 Silicon [Si]
• CPC Class Codes: H01L 2924/10272 Silicon Carbide [SiC]
• CPC Class Codes: H01L 2924/10329 : Gallium arsenide [GaAs]
• CPC Class Codes: H01L 2924/1033 : Gallium nitride [GaN]
• CPC Class Codes: H01L 2924/10338 : Indium gallium phosphide [InGaP]
• CPC Class Codes: H01L 2924/12032 : Schottky diode
• CPC Class Codes: H01L 2924/1305 : Bipolar Junction Transistor [BJT]
• CPC Class Codes: H01L 2924/13051 : Heterojunction bipolar transistor [HBT]
• CPC Class Codes: H01L 2924/13063 : Metal-Semiconductor Field-Effect Transistor [MESFET]
• CPC Class Codes: H01L 2924/13064 : High Electron Mobility Transistor [HEMT, HFET [heterostructure FET], MODFET]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/15153 : the die mounting substrate comprising a recess for hosting the device
• CPC Class Codes: H01L 2924/157 : with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2924/15787 : Ceramics, e.g. crystalline carbides, nitrides or oxides
• CPC Class Codes: H01L 2924/1579 : with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
• CPC Class Codes: H01L 2924/16195 : Flat cap [not enclosing an internal cavity]

Abstract

A high voltage semiconductor device can include a high voltage semiconductor device package that includes a wall defining a recess within the high voltage semiconductor device package. A high voltage semiconductor chip can be in the recess and a high voltage electric arc suppression material can be in the recess.

Claims

1. A high voltage semiconductor device comprising:

a high voltage semiconductor device package including a wall defining a recess within the high voltage semiconductor device package;

a high voltage semiconductor chip in the recess; and

a high voltage electric arc suppression material in the recess.

2. The high voltage semiconductor device of claim 1 wherein the high voltage electric arc suppression material comprises a group VIIA constituent element.

3. The high voltage semiconductor device of claim 1 wherein the high voltage electric arc suppression material comprises SF₆.

4. The high voltage semiconductor device of claim 1 wherein the high voltage semiconductor device comprises a Silicon Carbide (SiC) MOSFET.

5. The high voltage semiconductor device of claim 4 wherein the SiC MOSFET comprises a 20 amp SiC MOSFET wherein the high voltage semiconductor chip measures about 4 mm on a side thereof.

6. The high voltage semiconductor device of claim 4 wherein the SiC MOSFET comprises a 40 amp SiC MOSFET wherein the high voltage semiconductor chip measures about 8 mm on a side thereof.

7. The high voltage semiconductor device of claim 4 wherein the SiC MOSFET comprises a 100 amp SiC MOSFET wherein the high voltage semiconductor chip measures about 20 mm on a side thereof.

8. The high voltage semiconductor device of claim 1 wherein the high voltage semiconductor device package comprises metal, metal coated plastic, high temperature plastic, and/or ceramic.

9. The high voltage semiconductor device of claim 1 wherein the high voltage semiconductor device comprises a Si-Lateral-diffused MOS (LDMOS) transistor, a Bipolar junction transistor, a GaAs MESFET, a GaAs or GaAs/InGaP heterojunction bipolar transistor (HBTs), a SiC MESFET or a GaN HEMT.

10. The high voltage semiconductor device of claim 1 wherein the high voltage semiconductor device comprises a SiC Schottky Diode.

11. The high voltage semiconductor device of claim 1 wherein the high voltage semiconductor chip is configured for coupling to a voltage of at least about 600 Volts provided via a lead penetrating the wall.

12. The high voltage semiconductor device of claim 1 wherein the high voltage semiconductor chip is configured for coupling to a voltage of at least about 1200 Volts provided via a lead penetrating the wall.

13. The high voltage semiconductor device of claim 1 wherein the high voltage semiconductor chip is configured for coupling to a voltage of at least about 1700 Volts provided via a lead penetrating the wall.

14. The high voltage semiconductor device of claim 1 wherein the high voltage semiconductor chip is configured for coupling to a voltage of at least about 3400 Volts provided via a lead penetrating the wall.

15. The high voltage semiconductor device of claim 1 wherein a volume defined by the recess comprises about 750 mL or less.

16. The high voltage semiconductor device of claim 1 wherein a length of the recess comprises about 15 mm or less and a width of the recess comprises about 10 mm or less.

17. The high voltage semiconductor device of claim 1 wherein the high voltage semiconductor chip comprises a two terminal device.

18. The high voltage semiconductor device of claim 17 wherein a path through the high voltage electric arc suppression material from a first terminal configured to couple to a high voltage to a second terminal configured to couple to a reference voltage for the device is about 5 mm or less.

19. The high voltage semiconductor device of claim 1 wherein the high voltage semiconductor chip comprises a three terminal device.

20. The high voltage semiconductor device of claim 19 wherein a path through the high voltage electric arc suppression material from a first terminal configured to couple to a high voltage to a second terminal configured to couple to a reference voltage for the device is about 5 mm or less.

21. The high voltage semiconductor device of claim 1 further comprising:

a wire lead penetrating the wall and configured for electrically coupling a voltage of at least about 600 Volts to the chip; and

a submount having the chip mounted thereon, wherein the high voltage electric arc suppression material comprises a liquid or gas material having a dielectric breakdown voltage sufficient to prevent an electric arc from the wire lead to the submount.

22. The high voltage semiconductor device of claim 3 wherein the SF₆ is hermetically sealed in the recess.

23. The high voltage semiconductor device of claim 1 wherein the high voltage electric arc suppression material comprises SOF₂, SO₂F₂, and/or S₂F₁₀.

24. A high voltage Silicon Carbide (SiC) semiconductor device comprising:

a metal semiconductor device package including a wall defining an recess within the metal semiconductor device package;

a high voltage SiC semiconductor chip, including a bonding surface thereon, the chip coupled to a submount surface in the recess;

a wire lead electrically coupled to the bonding surface on the chip; and

SF₆ in the recess located between the wire lead at the bonding surface and the submount surface.

25. The high voltage SiC semiconductor device of claim 24 wherein a distance between the wire lead at the bonding surface and the submount surface comprises about 5 mm or less.

26. The high voltage SiC semiconductor device of claim 24 wherein the chip comprises a SiC MOSFET measuring about 4 mm on a side thereof.

27. The high voltage SiC semiconductor device of claim 24 wherein the chip is configured for coupling to a voltage of at least about 600 Volts provided via the wire lead penetrating the wall.

28. The high voltage SiC semiconductor device of claim 24 wherein the chip is configured for coupling to a voltage of at least about 1200 Volts provided via the wire lead penetrating the wall.

29. The high voltage SiC semiconductor device of claim 24 wherein a volume defined by the recess comprises about 750 mm³ or less.

30. The high voltage SiC semiconductor device of claim 24 wherein the chip is configured for coupling to a voltage of at least about 1700 Volts provided via the wire lead penetrating the wall.

31. The high voltage SiC semiconductor device of claim 24 wherein the chip is configured for coupling to a voltage of at least about 3400 Volts provided via the wire lead penetrating the wall.

32. A high voltage semiconductor device comprising:

a high voltage semiconductor device package including a wall defining an recess within the high voltage semiconductor device package;

a high voltage semiconductor chip in the recess; and

a high voltage electric arc suppression material in the recess comprising a liquid or gas material having a dielectric breakdown voltage sufficient to prevent an electric arc from the wire lead to the submount.

33. The high voltage semiconductor device according to claim 32 wherein the high voltage electric arc suppression material comprises SOF₂, SO₂F₂, SF₆, and/or S₂F₁₀.

34. A method of packaging a high voltage semiconductor device comprising:

providing a high voltage semiconductor device package, including a wall defining a recess within the high voltage semiconductor device package, to an atmosphere including a high voltage electric arc suppression material;

mounting a high voltage semiconductor chip in the recess while exposed to the atmosphere; and

sealing the high voltage semiconductor device package to enclose the high voltage electric arc suppression material with the high voltage semiconductor chip in the recess.

35. The method of claim 34 wherein the high voltage electric arc suppression material comprises a group VIIA constituent element.

36. The method of claim 35 wherein the group VIIA constituent element comprises fluorine.

37. The method of claim 35 wherein the group VIIA constituent element comprises Ununseptium.

38. The method of claim 34 wherein the high voltage electric arc suppression material comprises SF₆.

39. The method of claim 34 wherein the high voltage semiconductor device comprises a SiC MOSFET a Si-LDMOS transistor, a Bipolar junction transistor, a GaAs MESFET, a GaAs or GaAs/InGaP HBT, a SiC MESFET or a GaN HEMT.

40. The method of claim 39 wherein the SiC MOSFET comprises a 20 amp SiC MOSFET wherein the high voltage semiconductor chip measures about 4 mm on a side thereof.

41. The high voltage semiconductor device of claim 34 wherein the high voltage semiconductor device package comprises metal, metal coated plastic, high temperature plastic, and/or ceramic.

42. The high voltage semiconductor device of claim 34 wherein the high voltage semiconductor device package is configured for operation at a temperature of about 175 degrees Centigrade or greater.